In standard-cell-based VLSI design, fixed margins at cell boundaries are necessary to prevent short violations between adjacent transistors carrying different signals. However, these margins are redundant for most abutted cell pairs and incur non-negligible area overhead when accumulated across the chip. In this paper, we present a novel VLSI design optimization framework that eliminates redundant margins by strategically merging adjacent cells into margin-free cells (MF-cells), which preserve the same functionality with reduced area due to the removal of inter-cell margins. Precisely, we identify optimal cell pairs for merging from an initial standard-cell-based placement using a maximum weighted matching (MWM) algorithm. Each identified pair is replaced with an MF-cell and placed at an optimal position using a placement algorithm that minimizes wirelength and routing congestion. Compared to the conventional standard-cell-based design, we achieve on average 3.9% reduction in total cell area and 4.7% reduction in full chip area, leading to 2.7% reduction in total wire length and 2.1% improvement in timing performance while maintaining comparable power consumption. Our framework is a practical approach to achieve meaningful area and timing improvements, which is fully compatible with commercial standard-cell-based VLSI design flow.

Though using multi-bit flip-flop (MBFF) cells provide the benefit of saving dynamic power, its big cell size with many D/Q-pins inherently entails two critical limitations, which are (1) the loss of full flexibility in optimizing the wires connecting to the D/Q-pins in MBFFs and (2) the loss of selectively resizing i.e., controlling the driving strength of internal flip-flops in MBFFs to optimize timing. In this work, we propose a comprehensive solution to resolving those limitations through design and technology co-optimization (DTCO) in physical design flow. Specifically, to address limitation 1, given an input circuit with MBFF allocation and binding, at the post-placement stage we explore diverse layouts of MBFF cells with various D/Q-pin locations and rebind MBFF instances in the circuit to the MBFF cells that are the most suitable for minimizing the wirelength connecting D/Q-pins. Meanwhile, to address limitation 2, at the post-route stage we explore MBFF cell layouts of non-rectangle, precisely, L- and T-shape to control the driving strength of internal flip-flops selectively, by which we rebind MBFF instances with negative slack to the area-minimal rectangle or non-rectangle MBFF cells to optimize timing while increasing the power overhead minimally. Through experiments with benchmark circuits, it is shown that our DTCO driven MBFF rebinding method is able to produce the circuit implementations with 1.42% less wirelength in comparison with that produced by the state-of-the-art commercial EDA tool using MBFFs.

It is intuitively clear that a circuit to be implemented by selectively utilizing standard cells of various non-integer multiple-heights (NIMH) (e.g., mixed use of 6-track, 7.5-track, and 9-track cells) is able to provide a better opportunity in optimizing power, performance, and area over that by using cells of single-height only or of integer multiple-heights only. However, from the cell placement legalization point of view, the issues to be addressed for placement legalization on NIMH designs are very complex. And this paper primarily focuses on introducing novel ideas for row placement when utilizing NIMH cells, which involves determining the row pattern. The most inter-dependent and critical tasks, which are rather unique to the NIMH cell placement legalization problem, are ( task 1 ) for the cells of the same height, distributing and assigning them to a set of distinct rows on a die and ( task 2 ) determining the location of the rows containing cells of the same height. We solve the legalization problem by, starting from an initial row placement, iteratively solving the two tasks by formulating task 1 into an instance of row-capacity constrained network flow problem, followed by solving task 2 which leads to an optimal vertical displacement of the cells in the rows. Meanwhile, through experiments, it is shown that our network flow driven global cell assignment to rows for NIMH cell placement problem tightly linking the optimal determination of row location is able to reduce the total amount of cell displacements from the global (initial) placement by 9.5% and 51.2% in comparison with that produced by a greedy approach and the conventional state-of-the-art NIMH cell placement legalization method, respectively.

Traditionally, the synthesis of standard cells invariably assumes that the gear ratio (GR) between the gate poly pitch in the cells and the metal pitch of the first vertical metal layer (to be used for routing) over the gate poly is 1:1 for chip implementation. However, the scaling trend in sub-10nm node CMOS designs is that GR is changing from 1:1 to 3:2 or 4:3, which means the number and location of pin access points vary depending on the cell placement location, thereby causing hard-to-pin-access if the pin access points were aligned on the off-track routing pattern. This work overcomes the pin inaccessibility problem caused by non-1:1 GR in chip implementation. Precisely, we propose a non-1:1 GR aware DTCO (design and technology co-optimization) flow to generate cells with pin patterns that are best suited to the implementation of target design. To this end, we propose two new tasks to be installed in our DTCO framework: (1) from the existing cells optimized for 1:1 GR, we relocate their pin patterns amenable to non-1:1 GR, so that a maximal pin accessibility should be achieved; (2) we incrementally update the pin patterns of the cell instances with routing failures due to pin inaccessibility in the course of the DTCO iterations to produce the cells with best fitted pin patterns to the implementation of target design. We formulate task 1 into a problem instance of dynamic programming to find an optimal solution of pin positions, considering design rule and access conflict constraints while we solve task 2 by devising an assessment function on the pin accessibility enhanced by pin pattern extension to find out the most suitable direction for the extension. In the meantime, through experiments with benchmark circuits, it is shown that our DTCO methodology optimizing pin patterns amenable to non-1:1 GR is able to produce chip implementations with on average 5.88 × fewer routing failures at no additional wirelength, timing, and power cost.

This paper addresses the combined problem of the three core tasks, namely routing on the middle-of-line (MOL) layer, generating I/O pin patterns (PP), and allocating contacts over active gates (COAG) in cell layout synthesis with 7nm and below technology. As yet, the existing cell layout generators have paid partial or little attention to those tasks, even with no awareness of the synergistic effects. This work overcomes this limitation by proposing a systematic and tightly-linked solution to the combined problem to boost the synergistic effects on chip implementation. Precisely, we solve the problem in three steps: (1) fully utilizing the horizontal routing resource on MOL layer by formulating the problem of in-cell routing into a weighted interval scheduling problem, (2) simultaneously performing the remaining horizontal in-cell routing and PP generation on metal 1 layer through the COAG exploitation while ensuring the pin accessibility constraint, and (3) completing in-cell routing by allocating vertical routing resource on MOL layer. Through experiments with benchmark designs, it is shown that our proposed layout method is able to generate standard cells with on average 34.2% shorter total length of metal 1 wire while retaining pin patterns that ensure pin accessibility, resulting in the chip implementations with up to 72.5% timing slack improvement and up to 15.6% power reduction that produced by using the conventional best available cells. In addition, by using less wire and vias, our in-cell router is able to consistently reduce the worst delay of cells, noticeably, reducing the sum of setup time and clock-to-Q delay of flip-flops by 1.2% ∼ 3.0% on average over that by the existing best cells.