Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed toward leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP’s one-transistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators.

Biological systems are a great source of inspiration for developing novel computing technologies, as they exhibit favourable properties such as self-organisation and energy efficiency. The sheer complexity of these systems, however, makes developing such technologies both difficult and time-consuming. Tools providing the ability of emulating the behavior of complex systems, therefore become very essential. In this work, we present a method for emulating the behavior of electrical networks containing a coupling network with two-port coupling elements. Here, we make use of the wave digital concept due to the robustness and parallelism of the associated algorithms, which are closely related to the underlying electrical circuit. This work should serve as a basis for future implementations of close-to-biology neural networks.