Global routing is a critical stage in the VLSI design flow, aiming to provide a robust guide for detailed routing and serve as early design feedback for placement. Many approaches have leveraged GPU parallelization to achieve significant acceleration. However, with the fast-growing complexity of modern large-scale designs, recent GPU-accelerated maze routing algorithms, driven by the sweep operation, struggle to find solutions efficiently with limited GPU memory resources. In order to address this issue, this paper proposes a scalable, GPU-friendly sweep-based maze routing that requires significantly less memory and fewer kernel function calls while accelerating overall runtime. We introduce a sweep-sharing technique that allows multiple nets to be routed simultaneously within a single sweeping process, substantially reducing memory consumption and kernel launching overhead. We further propose an edge-level rip-up-andreroute technique that selectively reroutes only overflowed segments, preserving feasible parts of the solution to reduce runtime substantially. Experimental results on the latest ISPD’24 Contest benchmarks demonstrate that our GPUfriendly maze routing with sweep sharing can significantly improve the efficiency of the state-of-the-art GPU-accelerated maze router.

Power distribution networks (PDNs) are designed to deliver sufficient and stable power to circuit components. For high-speed printed circuit boards (PCBs), transient current pulses increasingly affect the power integrity in PDNs, potentially leading to circuit malfunction or component damage. Decoupling capacitors (decaps) are placed on a PDN to ensure power stability. Minimizing the number of decaps becomes critical and has been extensively studied. Traditional heuristic methods often search for unnecessary spaces or get stuck in local minima. To overcome these limitations, we propose an analytical approach that reformulates the nonlinear decap placement problem as an equivalent integer semidefinite programming model. We adopt techniques like integer relaxation and port reduction to improve scalability and minimize the usage of decaps by an adaptive optimization scheme. Experimental results on industrial benchmarks demonstrate that our analytical decap placer achieves better results than the state-of-the-art non-deterministic methods and even significantly outperforms the commercial tool in solution quality and runtime.

This paper proposes a power rail routing flow for advanced multi-layered printed circuit boards (PCBs) to optimize segment area and via usage while satisfying IR drop requirements. With increasing current/voltage demands in modern PCBs, ultra-wide power rails may consume most routing space and cause significant routing problems. We present an effective overlap-aware rail sizing technique to distribute routing spaces appropriately according to current/voltage demands and a resistance-aware A*-search algorithm to resolve overlapping regions by rail detouring. Experimental results show that our work significantly outperforms the state-of-the-art rail router in the metal area and runtime, achieving respective reductions of 49% and 28%, without any current/voltage violations.