This paper will introduce the concept of the Transparency cube in the extraction and testing of an embedded logic submodule. The algorithm presented can establish control of a submodule in a very small amount of CPU time, and it was found to perform extremely well when tested on cellular array topologies such as those which occur in systolic architectures. The program described detects if parts of a circuit are untestable and notifies the user as to where additional logic is necessary to make the circuit more transparent or testable. It also introduces controllability numbers for flexible signals (or subscripted D's) and a method by which an Exclusive Or gate (EXOR) is handled as a single gate in the controllability calculations. This is useful since controllability numbers do not represent well the difficulties encountered with reconvergent fanout.