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Linh-Tam Tran

dblp:303/4900 · DBLP profile ↗
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3ranked-venue papers
2as first author
3since 2021 · last 2026
0000-0002-9699-1747ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 3 · 2 first-author · 3 since 2021Graphics, computer vision, multimedia, augmented reality and games · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
2 papers
Efficient and distributed learning · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Machine learning › Efficient and distributed learning
model compression
1.722026
Post Training Quantization for Efficient Dataset Condensation · AAAI 2026
MST-compression: Compressing and Accelerating Binary Neural Networks with Minimum Spanning Tree · ICCV 2023
Machine learning › Efficient and distributed learning
dataset distillation
1.012026
Post Training Quantization for Efficient Dataset Condensation · AAAI 2026
Machine learning › Efficient and distributed learning › model compression › quantization
post-training quantization
1.012026
Post Training Quantization for Efficient Dataset Condensation · AAAI 2026
Machine learning › Efficient and distributed learning › model compression
quantization
1.012026
Post Training Quantization for Efficient Dataset Condensation · AAAI 2026
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
binary neural network accelerator
0.712023
MST-compression: Compressing and Accelerating Binary Neural Networks with Minimum Spanning Tree · ICCV 2023
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.712023
MST-compression: Compressing and Accelerating Binary Neural Networks with Minimum Spanning Tree · ICCV 2023

Methods — techniques the papers use, named apart from their topics

minimum spanning tree · 1.3learning-based channel reordering · 1.3XNOR operations · 1.3quantization-aware clustering · 1.0patch-based quantization · 1.0
YearPublicationVenuePosition
2026 Post Training Quantization for Efficient Dataset Condensation
abstract
Dataset Condensation (DC) distills knowledge from large datasets into smaller ones, accelerating training and reducing storage requirements. However, despite notable progress, prior methods have largely overlooked the potential of quantization for further reducing storage costs. In this paper, we take the first step to explore post-training quantization in dataset condensation, demonstrating its effectiveness in reducing storage size while maintaining representation quality without requiring expensive training cost. However, we find that at extremely low bit-widths (e.g., 2-bit), conventional quantization leads to substantial degradation in representation quality, negatively impacting the networks trained on these data. To address this, we propose a novel patch-based post-training quantization approach that ensures localized quantization with minimal loss of information. To reduce the overhead of quantization parameters, especially for small patch sizes, we employ quantization-aware clustering to identify similar patches and subsequently aggregate them for efficient quantization. Furthermore, we introduce a refinement module to align the distribution between original images and their dequantized counterparts, compensating for quantization errors. Our method is a plug-and-play framework that can be applied to synthetic images generated by various DC methods. Extensive experiments across diverse benchmarks including CIFAR-10/100, Tiny ImageNet, and ImageNet subsets demonstrate that our method consistently outperforms prior works under the same storage constraints. Notably, our method doubles the test accuracy of existing methods at extreme compression regimes (e.g., from 26.0% to 54.1% for DM at IPC=1), while operating directly on 2-bit images without additional distillation.
Linh-Tam Tran, Sung-Ho Bae
AAAI1
2026 Efficient dataset condensation with learnable color representation and subset matching
Linh-Tam Tran, Quang Hieu Vo, Maryam Qamar, Chaoning Zhang, Hui Yong Kim, Sung-Ho Bae
Knowl. Based Syst.1
2023 MST-compression: Compressing and Accelerating Binary Neural Networks with Minimum Spanning Tree
abstract
Binary neural networks (BNNs) have been widely adopted to reduce the computational cost and memory storage on edge-computing devices by using one-bit representation for activations and weights. However, as neural networks become wider/deeper to improve accuracy and meet practical requirements, the computational burden remains a significant challenge even on the binary version. To address these issues, this paper proposes a novel method called Minimum Spanning Tree (MST) compression that learns to compress and accelerate BNNs. The proposed architecture leverages an observation from previous works that an output channel in a binary convolution can be computed using another output channel and XNOR operations with weights that differ from the weights of the reused channel. We first construct a fully connected graph with vertices corresponding to output channels, where the distance between two vertices is the number of different values between the weight sets used for these outputs. Then, the MST of the graph with the minimum depth is proposed to reorder output calculations, aiming to reduce computational cost and latency. Moreover, we propose a new learning algorithm to reduce the total MST distance during training. Experimental results on benchmark models demonstrate that our method achieves significant compression ratios with negligible accuracy drops, making it a promising approach for resource-constrained edge-computing devices.
Quang Hieu Vo, Linh-Tam Tran, Sung-Ho Bae, Choong Seon Hong
ICCV2