This paper presents a 915 MHz ultra-low-power (ULP) receiver based on a single-path third-harmonic mixing (SPTHM) architecture. Unlike conventional multi-path sub-harmonic receivers that require precise multi-phase local oscillators (LOs), this work simplifies the receiver to a single-mixer path architecture by jointly optimizing the LO harmonic order and duty cycle. The receiver is driven by a 10%-duty-cycle LO operating at one-third of the carrier frequency ($f_{\mathrm {c}}$). Compared to the typical 50%-duty-cycle LO in the SPTHM configuration, the proposed receiver improves the conversion gain by 12.1 dB and noise figure (NF) by 5.2 dB. The architecture also exhibits a front-end NF variation of less than 1 dB across the 3%-13% LO duty-cycle range, thereby relaxing constraints on pulse generation. To facilitate ULP channel selection, a comparison-skipped frequency-locked loop (FLL) is used, consuming just$5~\mu $W. A high-Q IF amplifier with an improved active inductor load is incorporated to enhance in-band interference rejection, achieving 31 dB signal-to-interference ratio (SIR) at 5 MHz offset. Fabricated in a 65 nm CMOS, the receiver achieves a sensitivity of −86 dBm at 250 kbps data rate with a$39.4~\mu $W power consumption, including an on-chip LO. It indicates a competitive figure-of-merit (FoM) of 184 dB within a compact active area of 0.16 mm2.

This paper presents a 915MHz multi-channel receiver for ultra-low-power (ULP) applications. A sub-passive third-harmonic mixer is proposed to improve the front-end conversion performance at the ULP budget. Driven by the local oscillator (LO) that operates at one-third of the RF carrier frequency with a duty cycle of about 10%, the proposed mixer improves the front-end’s noise figure (NF) to 15dB while reducing the LO power consumption by three times. The mixer also alleviates the requirement for LO phase accuracy. With the LO duty cycle ranging from 4% to 14%, the variation of the mixer performance is less than 10%, which allows a simple pulse generation approach without a precise duty cycle control circuit, thereby saving power consumption. A low-power frequency-locked loop (FLL) with a 196kHz tuning step facilitates channel selection. Additionally, a high-Q intermediate-frequency (IF) amplifier with an active inductor is used to suppress in-band interference and noise bandwidth. Implemented in a 65nm CMOS process and based on post-simulation results, the receiver achieves a sensitivity of −88dBm while consuming 40µW at a 250kb/s data rate. The receiver also performs an improved figure-of-merit (FoM) of 186dB with 26dB interference tolerance and a compact active area of 0.16mm2.

A reference double-sampling phase-locked-loop-based (RDSPLL-based) multi-phase clock generator (MPCG) for DDR PHY is presented. The reference double-sampling architecture is utilized to achieve low phase noise. A CDAC-embedded voltage offset calibration is proposed to reduce jitter and reference spur, and a CMP-ADC hybrid phase detector is adopted to accelerate the locking process. Fabricated in 65nm, the proposed MPCG achieves better than 1° phase accuracy with a 100MHz reference clock. The reference spur is reduced from -56dBc to -80dBc and the locking time is reduced from 10.5us to 1.6us. The measured RMS jitter is 674fs at 2.4GHz with 3.43mW, yielding the FOMJitter-Nof -251.9dB.

This paper presents a reference double-sampling phase-locked loop (RDSPLL) that integrates frequency multiplication and octa-phase clock generation into a single system, significantly reducing power consumption. A differential ring oscillator (DRO) is employed to generate octa-phase clocks with high phase accuracy. The reference double-sampling technique extends the loop bandwidth, effectively suppressing phase noise from the ring oscillator and thereby reducing jitter. To achieve accurate and efficient phase error detection, we proposed a novel offset-compensated hybrid phase detector (OCH-PD), featuring an offset calibration and a comparator-ADC hybrid quantizer. The offset calibration utilizes the CDAC to dynamically compensate for the mismatch in double-sampling, improving jitter and spur performance. The hybrid quantizer supports dynamic mode switching based on different locking states: during the coarse frequency locking phase, it operates in the ADC mode to accelerate the locking process; once a stable lock is achieved, it switches to the comparator mode to enable low-power, high-speed quantization. Fabricated in a 65-nm CMOS process, the prototype achieves 674 fs RMS jitter at 2.4 GHz while consuming only 3.43 mW, resulting in a$\text {FOM}_{\text {Jitter-N}}$of -251.9 dB. With offset calibration, the reference spur at 100 MHz is suppressed from -56 dBc to -80 dBc, and the jitter is reduced from 1.42 ps to 674 fs. The locking time improves from$10.5~{\mu }$s to$1.6~{\mu }$s using the hybrid quantizer. The eight-phase accuracy remains better than 1° over the frequency range of 2-2.8 GHz.

Wireless sensing technology based on channel state information (CSI) has broad application prospects in human–computer interaction, smart homes, and other fields due to its advantages, which include no special equipment deployment, no privacy leakage, and no light intensity and line of sight influence. The existing studies have achieved satisfactory recognition accuracy for human localization or activity information. However, many applications need to recognize not only the activity of humans but also the location of humans. Therefore, multidimensional information recognition for human targets has become an urgent problem to be solved. For this problem, a multidimensional information recognition algorithm for human targets based on CSI decomposition (called the CD-MDIR algorithm) is proposed. Specifically, we first decompose the CSI time series into dynamic location CSI (DLC) components affected by human location and dynamic activity CSI (DAC) components affected by human activity, according to the independent characteristics of the influence of human location and activity on CSI. Then, the linear discriminant analysis (LDA) algorithm is used to transform the DLC component to enhance the location information, and the features of the DAC component are extracted to enhance the activity information. Finally, we designed a long short-term memory (LSTM) multidimensional information recognition network that successively recognizes the location and activity information of humans. Experimental results show that the proposed CD-MDIR algorithm achieves both higher localization and activity recognition accuracy.

With the emergence of tools for extracting CSI data from commercial WiFi devices, CSI-based device-free activity recognition technology has developed rapidly and has been widely used in security monitoring, smart home, medical monitoring, and other fields. However, the existing CSI-based activity recognition algorithms need a large number of training samples to obtain the ideal recognition accuracy. To solve the problem, an attention-based bidirectional LSTM method using multidimensional features (called MF-ABLSTM method) is proposed. In this method, the signal preprocessing and continuous wavelet transform algorithms are used to construct time-frequency matrix, the sample entropy is used to characterize the statistical feature of CSI amplitudes, the energy difference at a fixed time interval is used to characterize the time-domain feature of activities, and the energy distribution of different frequency components is used to characterize the frequency-domain feature of activities. By expanding the training samples with the proposed tensor prediction algorithm, the accurate activity recognition can be realized with only a few samples. A large number of experiments verify the good performance of MF-ABLSTM method.