We present FlexiFlow, a lifetime-aware design framework for item-level intelligence (ILI) where computation is integrated directly into disposable products like food packaging and medical patches. Our framework leverages natively flexible electronics which offer significantly lower costs than silicon but are limited to kHz speeds and several thousands of gates. Our insight is that unlike traditional computing with more uniform deployment patterns, ILI applications exhibit 1000× variation in operational lifetime, fundamentally changing optimal architectural design decisions when considering trillion-item deployment scales. To enable holistic design and optimization, we model the trade-offs between embodied carbon footprint and operational carbon footprint based on application-specific lifetimes. The framework includes: (1) FlexiBench, a workload suite targeting sustainability applications from spoilage detection to health monitoring; (2) FlexiBits, area-optimized RISC-V cores with 1/4/8-bit datapaths achieving 2.65× to 3.50× better energy efficiency per workload execution; and (3) a carbon-aware model that selects optimal architectures based on deployment characteristics. We show that lifetime-aware microarchitectural design can reduce carbon footprint by 1.62×, while algorithmic decisions can reduce carbon footprint by 14.5×. We validate our approach through the first tape-out using a PDK for flexible electronics with fully open-source tools, achieving 30.9\,kHz operation. FlexiFlow enables exploration of computing at the Extreme Edge where conventional design methodologies must be reevaluated to account for new constraints and considerations. FlexiFlow is available at https://github.com/harvard-edge/FlexiFlow.

RISC-V FPGA, also written RVfpga, is a set of two freely available courses developed by the authors and Imagination Technologies that enable users to understand and use the RISC-V instruction set architecture (ISA), a commercial RISC-V core and system, and the RISC-V ecosystem. The first course, RVfpga, includes comprehensive instructions, tools, and labs for targeting a commercial RISC-V processor to a field programmable gate array (FPGA) and then using and expanding it to learn about computer architecture, digital design, embedded systems, system-on-chip (SoC) design, and programming. The topics covered include targeting the RISC-V SoC to an FPGA, programming in C and RISC-V assembly, running programs in simulation or, optionally, in hardware, using peripherals and adding new ones to the SoC, and analyzing and modifying the RISC-V core and memory system, including adding new instructions to the core. The follow-on course, RVfpga-SoC, shows how to build a RISC-V SoC from building blocks and then run the Zephyr real-time operating system (RTOS) on it. At the completion of these courses, users will have a working RISC-V system and have hands-on experience exploring and using both the RISC-V SoC and the RISC-V toolchain, including compilers and simulators.