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Liting Shen

dblp:304/0731 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 78% Processor architecture and microarchitecture · 22%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › computer arithmetic
bit-serial arithmetic
0.512021
RACER: Bit-Pipelined Processing Using Resistive Memory · MICRO 2021
Memory systems › processing-in-memory
computing-in-memory
0.512021
RACER: Bit-Pipelined Processing Using Resistive Memory · MICRO 2021
Memory systems
processing-in-memory
0.512021
RACER: Bit-Pipelined Processing Using Resistive Memory · MICRO 2021
Memory systems › non-volatile memory
resistive memory
0.512021
RACER: Bit-Pipelined Processing Using Resistive Memory · MICRO 2021
Memory systems
emerging memory technologies
0.112021
RACER: Bit-Pipelined Processing Using Resistive Memory · MICRO 2021
Memory systems
non-volatile memory
0.112021
RACER: Bit-Pipelined Processing Using Resistive Memory · MICRO 2021

Methods — techniques the papers use, named apart from their topics

boolean primitives · 0.5bit-pipelined processing · 0.5
YearPublicationVenuePosition
2021 RACER: Bit-Pipelined Processing Using Resistive Memory
abstract
To combat the high energy costs of moving data between main memory and the CPU, recent works have proposed to perform processing-using-memory (PUM), a type of processing-in-memory where operations are performed on data in situ (i.e., right at the memory cells holding the data). Several common and emerging memory technologies offer the ability to perform bitwise Boolean primitive functions by having interconnected cells interact with each other, eliminating the need to use discrete CMOS compute units for several common operations. Recent PUM architectures extend upon these Boolean primitives to perform bit-serial computation using memory. Unfortunately, several practical limitations of the underlying memory devices restrict how large emerging memory arrays can be, which hinders the ability of conventional bit-serial computation approaches to deliver high performance in addition to large energy savings.
Minh S. Q. Truong, Deanyone Su, Liting Shen, Alexander Glass, L. Richard Carley, James A. Bain, Saugata Ghose
MICRO4