Artificial Intelligence hardware accelerators are pervading the chip market. Most of the time, they are third-party IPs integrated by silicon manufacturers. As a consequence, their design may be obfuscated, which can introduce issues from a manufacturing testing perspective. This paper illustrates how to effectively and efficiently select the most appropriate functional stress stimuli for Artificial Intelligence (AI) Hardware (HW) Accelerators embedded in System-on-Chip (SoC). The proposed methodology is netlist independent; and it is based on both current measurements from the real chip and architectural evaluations. These ingredients are heuristically used to rank and sift the optimal functional patterns to apply along the Burn-In (BI) phase. Experimental results on two different Automotive SoCs manufactured by STMicroelectronics, demonstrate the effectiveness and efficiency of the proposed method.

In modern automotive system-on-chip (SoC) designs, large embedded flash memories have become a standard feature. Since they occupy a significant percentage of the die area, their impact on the SoCs’ overall yield is substantial, making them a critical component in the production process. Embedded memories are then deeply tested to unsure their reliability. The data collected through these tests are fundamental to chip designers and test engineers to iron out their designs and understand the most common failure mechanisms. A common approach for data collection is the generation of bitmaps based on the gathering of individual fail coordinates in a list-based fashion. Other more efficient compaction or compression approaches exist and all these approaches can use dedicated internal memories to store the result of a given test. Unfortunately, all the methods currently found in the literature do not allow diagnostic data retention along multiple tests, requiring constant and time-consuming communications with the external tester, increasing the test cost for the manufacturers. This article presents an on-chip algorithm to compact and retain diagnostic information from multi-step embedded memories testing. The foundation of this work lies in an efficient shape recognition and encoding algorithm. The collected information is stored in a dedicated nonvolatile on-chip memory. Information about the tests that generated a given set of fault shapes is also encoded in this dedicated diagnostic memory, enabling manufacturers to collect all the diagnostic information at the end of their test flow. Experimental results on over 110 Automotive SoCs made by Infineon TM show that using the proposed approach, 100% of the diagnostic information of devices undergoing a standard automotive-grade test flow is permanently encodable in a limited 24 KB diagnostic space while also consistently reducing the total test time of up to 53.8% with respect to traditional list-based approaches.

Embedded memories are an essential component of modern System-on-Chips (SoCs). As memory requirements are constantly increasing, embedded memories occupy a significant percentage of the die area and are one of the main contributors to the yield of the devices. Manufacturers must conduct thorough testing to assess the reliability of their products, particularly in safety-critical environments like automotive applications. A typical automotive-grade memory test flow comprises several tests under varying conditions, including temperature and operating frequency. The SoC under test executes these tests, and they typically generate an extensive amount of diagnostic data that needs to be exported to the external world in time-consuming communications with the external testers. The computationally easiest way to encode the diagnostic data is through a list-based method, in which each single fault is logged individually, but is not particularly efficient with huge number of faults. This paper presents an optimized on-chip fault encoding algorithm that combines an efficient fault shape encoding method with only the encoding of the differences between each test. Experimental results collected in a simulation environment, where 10,000 devices were modeled to realistically represent fault evolution between consecutive memory tests, demonstrate an average reduction of 66.99% in diagnostic memory space requirements compared to previous State-Of-The-Art (SOTA) solutions.

Embedded System-on-Chip (SoC) memory requirements in the Automotive industry are constantly growing. For this reason, memories occupy a significant part of Automotive SoC’s die area, increasing the defect probability inside the embedded storage. Automotive SoC manufacturers need to deeply test their embedded memories as they are one of the significant contributors to the yield of their devices. The test effort increases for the characterization of new technologies and new families of devices that need to be characterized by the manufacturers. These tests generate a massive quantity of diagnostic information that is incredibly valuable for designers and technology experts. This diagnostic information can be analyzed to identify and correct possible weaknesses and misbehavior. The easiest way to collect memory diagnostic information consists of failure bitmaps in which each fault is saved as coordinates. This method is the simplest solution to implement. However, logging the coordinates of every fault may generate an unmanageable quantity of data. This problem is exacerbated when there is an on-chip limitation on the amount of data that can be saved or transmitted to the external world.This paper presents an optimized on-chip compression algorithm that allows to reduce the required on-chip memory to store diagnostic information during embedded memory testing. This solution allows the reconstruction of a failure bitmap, generating a topological representation of the density of the failings bits in the embedded on-chip memory. The proposed approach effectively reduces the used storage to a fraction with respect to the one used by the original failing bitmap. The algorithm uses a coordinates-based approach, in which the memory is logically divided into equally divided sectors. The small time overhead introduced by the algorithm is compensated by the ability to achieve optimal space utilization.

With the capability improvements in modern Systemon-Chips (SoCs), the complexity of SoCs is increasing. Thus, manufacturers are investing heavily in designing and testing their devices. This complexity is causing a continuous expansion in the size of embedded memory structures. As a result of the shrinking dimensions of the transistors, memories are increasingly susceptible to Multiple Bit Upsets due to cosmic radiations.Testing memories requires more details about the internal hardware configurations. However, these details are not provided to the final customer, who is left with inexplicable effects.This paper proposes a new method to reconstruct architectural details from embedded SoC memories. This method extracts memory design parameters from Multiple Bit Upsets (MBUs) generated through a single irradiation test. The algorithm was tested on around 5,500 randomly generated memories. Each memory was injected with 100 Multiple Event Upsets (MEUs). The algorithm was set to test for each memory 20, 40, 60, 80, and 100 MEUs to validate the proposed approach. Alongside the correct memory design configuration (MDC), the algorithm found other possible MDCs. The quantity of these equivalent configurations decreased with the increment of the considered MEUs. This number decreased to an average of 2 equivalent MDCs when considering 100 MEUs.

Embedded memories in Automotive Systems-on-Chip usually occupy a large die area portion. Consequently, their defectivity can strongly impact production yield for any automotive device. Along with the technology ramp-up phase and for statistical process control reasons during volume production, it is a good automotive industry practice to collect diagnostic information in addition to pure testing data. Designers and technology experts must receive accurate diagnostic results from failing devices to react to misbehavior by identifying and correcting the related issues at their source and drawing correct repair strategy conclusions. A commonly used approach resorts to the generation of failure bitmaps based on collecting all failing bits coordinates to be sent one by one to the tester. More efficiently, the encountered faults can be compacted or compressed in on-chip memory resources to be retrieved by the tester at the end of the memory test.This paper presents an on-chip method to compact diagnostic information during embedded memory testing. More specifically, the method is applied to diagnose embedded FLASH memories. This strategy permits the reconstruction of failure bitmaps without any loss, while compression approaches obtain an approximation. The proposed method uses a fraction of the memory requested by a coordinate-based bit mapping approach and is comparable to compression methods. At the cost of a moderate test time overhead, the proposed strategy permits dramatically increasing the number of devices that can be fully diagnosed without any bitmap reconstruction loss. Most failing devices in a real embedded FLASH production scenario were diagnosed after a single transfer from on-chip to the tester host computer.

Electronics employed in modern safety-critical systems require severe qualification during the manufacturing process and in the field, to prevent fault effects from manifesting themselves as critical failures during mission operations. Traditional fault models are not sufficient anymore to guarantee the required quality levels for chips utilized in mission-critical applications. The research community and industry have been investigating new test approaches such as device-aware test, cell-aware test, path-delay test, and even test methodologies based on the analysis of manufacturing data to move the scope from OPPM to OPPB. This special session presents four contributions, from academic researchers and industry professionals, to enable better chip quality. We present results on various activities towards this objective, including device-aware test, software-based self-test, and memory test.