This paper demonstrates the design process and performance prediction of a cryogenic 22 nm FDSOI circuit using a design-oriented model. The simplified EKV model is adopted to capture IV characteristics of short-channel transistors, for which parameters are extracted from cryogenic measurement of commercial FDSOI MOSFETs. When applied to a complete circuit, the model accurately predicts performances at various back-gate voltages and temperatures, achieving less than 1 % average absolute error. This validates the presented analytical approach, even under the stringent requirements of low-temperature operation, paving the way to exploiting rather than enduring cryogenic temperature effects on CMOS designs.

The output conductance and transconductance are key small-signal parameters that typically set the dc gain of amplifiers. Although the transconductance can be modelled simply and accurately, modeling the output conductance over a large range of bias and geometries is much more challenging. In advanced technologies the self-gain has shrunk dramatically, while the transit frequency has increased significantly. The de-signer can hence choose a transistor length longer than minimal achieving a higher dc gain while still meeting the frequency specifications. Now, how much longer than minimum should he choose? We will try to answer this question by proposing a simple output conductance model that is valid over a wide range of bias and geometries. The model is validated by simulations for a 28-nm FDSOI CMOS process.

Energy efficiency is of utmost importance in modern applications. Power consumption optimisation could be improved by a comprehensive analytical modeling of the characteristics of critical blocks in a system. Dynamic range (DR) has a strong effect on the power consumption of analog circuits, and is determined by circuit non-linearity and noise level. Noise is well modelled even in deep sub-micron technologies, yet there is a lack of analysis and modeling of the non-linearity. An analytical MOSFET differential pair non-linearity model is presented in this work. The proposed model is universal to a wide range of technologies from long to ultra-deep sub-micron devices, and is valid for all operating regions as it is based on the EKV MOSFET model. Furthermore, a model including drain-voltage-induced non-linearity is also developed, and a concise 3dB input intercept point (IIP3) formula incorporating the drain induced non-linearity in terms of the voltage gain is presented. The proposed models are validated with DC and AC simulations and measurements.

The$G_{m}/I_{D}$approach has proven to be an efficient technique for the design of low-power analog circuits even in advanced technology nodes. It has already been shown that the normalized$G_{m}/I_{D}$is actually a universal figure-of-merit (FoM) that is independent of technology and of device geometry. In addition, we will show experimentally in this paper that the normalized$G_{m}/I_{D}$is also almost independent of temperature even down to cryogenic temperatures. Analog designers are currently struggling to design circuits that have to operate at cryogenic temperatures for quantum computing application. This is because the compact models available in the physical design kit (PDK) provided by foundries fail at cryogenic temperatures. While the models need to be improved to account for low-temperature physics, the$G_{m}/I_{D}$approach can help designing cryo-CMOS analog circuits. In this paper we will show how it can be used for the design of a simple low-noise amplifier in a 16 nm FinFET technology taking advantage of the temperature independence of$G_{m}/I_{D}$.

This paper establishes the close relation that exists between the Fano noise suppression factor$F$and the$G_{m}/I_{D}$FoM showing that$F$is proportional to the product of the thermal noise excess factor$\gamma_{n}$and the normalized$G_{m}/I_{D}$function. Taking advantage of the EKV model formulation of the normalized$G_{m}/I_{D}$and$\gamma_{n}$in terms of the inversion coefficient$IC$, a simple expression of$F$versus$IC$for long and short channel transistors is derived. The proposed model of$F$versus$IC$for short-channel devices is validated against measurement from various CMOS technologies. Additional measurements of$G_{m}/I_{D}$performed on FDSOI devices down to cryogenic temperatures show that it is a universal FoM almost independent of temperature. Since$F$is proportional to$G_{m}/I_{D},\ F$should also be almost temperature independent. The proposed model constitutes a good starting point for having a model of the MOSFET white noise that is valid in all regions of operation and down to cryogenic temperatures.

The$G_{m}/I_{D}$approach has proven to be an efficient technique for the design of low-power analog circuits. Until now it was mostly demonstrated on older CMOS technology nodes. In this paper we will show that the$G_{m}/I_{D}$methodology still holds for advanced technologies using the simplified EKV model which only requires 4 parameters for bulk and 5 for FDSOI. We will start with a brief presentation of the simplified EKV model highlighting how the normalization process can strip-off most of the technology dependence. Then we will introduce the concept of inversion coefficient$IC$and show that the normalized$G_{m}/I_{D}$only depends on$IC$and a parameter$\lambda_{c}$accounting for velocity saturation. Then we will show how to extract the few parameters needed from data either generated from the PDK or from measurements. We then will illustrate the methodology by a design example of an OTA in a 22nm FDSOI technology. The design is then validated by simulations using the founder PDK using the full BSIM-IMG compact model demonstrating an excellent agreement between the simulation results and the specifications despite the simplicity of the model and the methodology.