EDBT 2026 Demo / reviewers in the wild / expert
Makoto Eiki
dblp:305/4477
· DBLP profile ↗
4ranked-venue papers
2as first author
4since 2021 · last 2023
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-author · 4 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous EffectsabstractStatistical wafer-level variation modeling is an attractive method for reducing the measurement cost in large-scale integrated circuit (LSI) testing while maintaining the test quality. In this method, the performance of unmeasured LSI circuits manufactured on a wafer is statistically predicted from a few measured LSI circuits. Conventional statistical methods model spatially smooth variations in wafer. However, actual wafers may have discontinuous variations that are systematically caused by the manufacturing environments, such as shot dependence. In this study, we propose a modeling method that considers discontinuous variations in wafer characteristics by applying the knowledge of manufacturing engineers to a model estimated using Gaussian process regression. In the proposed method, the process variation is decomposed into the systematic discontinuous and global components to improve the estimation accuracy. An evaluation performed using an industrial production test dataset shows that the proposed method reduces the estimation error for an entire wafer by over 33% compared to conventional methods. Takuma Nagao, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, Michihiro Shintani |
ASP-DAC | 4 |
| 2023 | Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble LearningabstractAlthough automotive semiconductors must comply with the standard dynamic part average testing (DPAT) defined by the Automotive Electronics Council, it remains challenging to detect outliers that deviate from the spatial trend within a wafer. Outlier detection using Gaussian process (GP) regression has recently been proposed and outperformed DPAT. However, the detection performance degrades when faulty large-scale integrations are densely included in the regression. Furthermore, the applicable test items are limited because of the long computation time for regression. We propose an outlier detection method by applying ensemble learning to GP regression for simultaneously improving the detection performance and shortening the learning time. Experimental results on industrial production test data demonstrate that the proposed method improves the robustness against latent faulty chip detection by 15.6% while reducing the computation time by 98.6% compared with the conventional GP-based method. Makoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Takashi Sato 0001, Michihiro Shintani |
ITC | 1 |
| 2022 | Accurate Failure Rate Prediction Based on Gaussian Process Using WAT DataabstractIn this paper, we propose a novel method for predicting the characteristic failure rate from a small amount of data with high accuracy using the posterior distribution of the Gaussian process. In the proposed method, using multiple lots, a local pattern on the wafers is estimated from the measurement results of the target-probe test item for failure-rate prediction. For failure-rate prediction, the global trend of each wafer is predicted by the Gaussian process using WAT data and superimposed on the local pattern. The proposed method derives the failure rate of each die based on the posterior distribution using the Gaussian process in the global trend calculation. Experiments using industrial semiconductor manufacturing data demonstrate that the proposed method can reduce the estimation error by approximately 70% compared to a conventional method. Makoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Michihiro Shintani |
ITC | 1 |
| 2021 | Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian ProcessabstractWafer-level performance prediction has been attracting attention to reduce measurement costs without compromising test quality in production tests. Although several efficient methods have been proposed, the site-to-site variation, which is often observed in multi-site testing for radio frequency circuits, has not yet been sufficiently addressed. In this paper, we propose a wafer-level performance prediction method for multi-site testing that can consider the site-to-site variation. The proposed method is based on the Gaussian process, which is widely used for wafer-level spatial correlation modeling, improving the prediction accuracy by extending hierarchical modeling to exploit the test site information provided by test engineers. In addition, we propose an active test-site sampling method to maximize measurement cost reduction. Through experiments using industrial production test data, we demonstrate that the proposed method can reduce the estimation error to 1/19 of that obtained using a conventional method. Moreover, we demonstrate that the proposed sampling method can reduce the number of the measurements by 97% while achieving sufficient estimation accuracy. Michihiro Shintani, Mian Riaz-ul-haque, Michiko Inoue, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki |
ITC | 6 |