Binary polynomial multipliers impact the overall performance and cost of elliptic curve cryptography (ECC) systems. Multiplication algorithms with subquadratic computational complexity are widely used to reduce area requirements and improve the delay of ECC cryptographic hardware. This work presents an elliptic curve scalar point multiplication (SPM) processor implementation using a novel classification of improved overlap-free multipliers targeting applications in the Internet of Things (IoT) devices. The proposed multipliers combine the advantages of fewer partial products and the overlap-free reconstructions which results in better recurrence and improved performance. The proposed multipliers and point multiplication hardware were designed, implemented, and tested on FPGA. The implemented processor presents a reasonable trade-off between speed and area consumption, and the design compares favorably with the previous designs in terms of area-delay product.

Novel binary polynomial multipliers have been designed using M-term overlap-free Karatsuba multiplication (OFKM), where$M$is 5–8. The proposed designs were realized in digital hardware and implemented on field-programmable gate array (FPGA) and the best value of$M$was selected and presented for common National Institute of Standards and Technology (NIST) operand sizes from 64 to 571 bits. The implemented hardware designs use a hybrid approach that combines a given M-term overlap-free Karatsuba multipliers with two-term splitting to reduce the need for zero-padding in the final recurrent stages. Compared to the traditional M-term Karatsuba multipliers, the proposed overlap-free implementations offer reductions in delay and area-delay product (ADP). The proposed designs also compare favorably to previous implementations of binary polynomial multipliers. Their favorable characteristics make the proposed overlap-free Karatsuba polynomial multipliers viable options for use in cryptographic systems where speed is a significant consideration and hardware resource consumption must be limited.

Finite field multiplication is a fundamental and frequently used operation in various cryptographic circuits and systems. Because of its high complexity, this operation generally determines the overall complexity and cost of these systems. Therefore, finite field multipliers and their hardware implementation have received considerable attention from researchers. This article proposes a methodology to design an efficient Galois field multiplier. First, space and time complexities for theoretical and field-programmable gate array (FPGA) implementations of M-term Karatsuba-like finite field multipliers were obtained. In addition, an algorithm was developed to obtain an efficient design based on a composite M-term Karatsuba-like multiplier. Furthermore, the proposed multipliers were verified and implemented on various FPGA devices, and implementation results were presented. Reported device utilization and latency indicated that the proposed multiplier is roughly 26% faster and 15% more efficient in the area–delay product compared to the standard Karatsuba multiplier. Moreover, comparison with state of the art also indicated that the proposed design is leading in terms of effectiveness and speed.

A physical unclonable function (PUF) is a promising lightweight circuit that provides security and authentication capability for electronic devices with low computational resources. Among various PUFs, the bistable ring PUF (BR-PUF) is considered one of the robust configurations. However, it has been shown that the challenge-response pairs (CRPs) from BR-PUF are vulnerable to statistical machine learning (ML) attacks, such as k-junta learning, support vector machine (SVM), and logistic regression (LR). In this article, we first show that the k-junta attack can break CRPs from the BR-PUF. Then, we present a hybrid chaotic-BR-PUF structure that obfuscates the BR-PUF response with the nonlinearized chaotic response. The proposed PUF structure has been implemented and experimentally evaluated on Xilinx Artix-7 FPGA, and the PUF measurements were captured. The proposed PUF was tested with a powerful statistical method developed using k-junta-based learning to confirm its strength against such attacks and evaluated using CRPs collected. The proposed PUF provides better resistance against ML attacks and reduces the learning accuracy to 50%–60% compared with previously proposed PUFs.