Routability estimation identifies potentially congested areas in advance to achieve high-quality routing solutions. To improve the routing quality, this paper presents a deep learning-based congestion estimation algorithm that applies the estimation to a global router. Unlike existing methods based on traditional compressed 2D features for model training and prediction, our algorithm extracts appropriate 3D features from the placed netlists. Furthermore, an improved RUDY (Rectangular Uniform wire DensitY) method is developed to estimate 3D routing demands. Besides, we develop a congestion estimator by employing a U-net model to generate a congestion heatmap, which is predicted before global routing and serves to guide the initial pattern routing of a global router to reduce unexpected overflows. Experimental results show that the Pearson Correlation Coefficient (PCC) between actual and our predicted congestion is high at about 0.848 on average, significantly higher than the counterpart by 21.14%. The results also show that our guided routing can reduce the respective routing overflows, wirelength, and via count by averagely 6.05%, 0.02%, and 1.18%, with only 24% runtime overheads, compared with the state-of-the-art CUGR global router that can balance routing quality and efficiency very well. In particular, our work provides a new generic machine learning model for not only routing congestion estimation demonstrated in this paper, but also general layout optimization problems.

Reference placement is promising to handle the increasing complexity in PCB design. We model the netlist into a graph and use a subgraph matching algorithm to find the isomorphism of the placed template in component combination to reuse the placement. The state-of-the-art VF3 algorithm can achieve high matching accuracy while suffering from high computation time in large-scale instances. Thus, we propose the D2BS algorithm to guarantee matching quality and efficiency. We build and filter the candidate set (CS) according to designed features to construct the CS structure. In the CS optimization, a graph diversity tolerance strategy is adopted to achieve inexact matching. Then, hierarchical match is developed to search the template embeddings in the CS structure guided by branch backtracking and matched nodes snatching. Experimental results show that D2BS outperforms VF3 in accuracy and runtime, achieving 100% accuracy on PCB instances.

With feature size scaling and complexity increase of circuit designs, hotspot detection has become a significant challenge in the very-large-scale-integration (VLSI) industry. Traditional detection methods, such as pattern matching and machine learning, have been made a remarkable progress. However, the performance of classifiers relies heavily on reference layout libraries, leading to the high cost of lithography simulation. Querying and sampling qualified candidates from raw datasets make active learning-based strategies serve as an effective solution in this field, but existing relevant studies fail to take sufficient sampling criteria into account. In this paper, embedded in pattern sampling and hotspot detection framework, an entropy-based batch mode sampling strategy is proposed in terms of calibrated model uncertainty and data diversity to handle the hotspot detection problem. Redundant patterns can be effectively avoided, and the classifier can converge with high celerity. Experiment results show that our method outperforms previous works in both ICCAD2012 and ICCAD2016 Contest benchmarks, achieving satisfactory detection accuracy and significantly reduced lithography simulation overhead.