Demo Data from EDBT 2026 / reviewers in the wild / expert
Raees Kizhakkumkara Muhamad
dblp:305/9239
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2022
0000-0001-8010-8940ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021Human-computer interaction and ubiquitous computing · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 67% Electronic design automation · 33% | |
| Computer graphics and multimedia
1 paper |
Image and video coding · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › high-level synthesis › arithmetic-level optimization
bit-width optimization |
0.5 | 1 | 2021 | Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation · DAC 2021 |
Integrated circuit design
digital signal processing circuits |
0.5 | 1 | 2021 | Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation · DAC 2021 |
Integrated circuit design
low-power circuit design |
0.5 | 1 | 2021 | Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation · DAC 2021 |
Image and video coding
video compression |
0.1 | 1 | 2021 | Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation · DAC 2021 |
Methods — techniques the papers use, named apart from their topics
scaling information propagation · 1.0fixed-point scaling · 1.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Quality evaluation of the JPEG Pleno Holography Call for Proposals responseabstractAt its 93rd meeting, JPEG received the responses to the Call for Proposals on JPEG Pleno holography. This activity will lead to the first standardized coding solution for digital holograms. This paper describes the quality evaluation process, existing out of a subjective evaluation study and an objective evaluation based on preselected quality metrics. It also includes a critical evaluation of the challenges encountered when performing quality evaluation of holographic content. Based on the evaluation of the response, the JPEG committee was able to select a very reliable coding solution that depicted a performance well beyond that of the selected anchors. João Prazeres, Antonin Gilles, Raees Kizhakkumkara Muhamad, Tobias Birnbaum, Peter Schelkens, António M. G. Pinheiro |
QoMEX | 3 |
| 2021 | Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information PropagationabstractThe Fast Fourier Transform (FFT) is an efficient algorithm widely used in digital signal processing to transform between the time domain and the frequency domain. For fixed-point VLSI implementations, dynamic range growth inevitably occurs at each stage of the FFT operation. However, current methods either waste bitwidth or consume excessive resources when dealing with the dynamic range growth issue. To address this issue, we propose an efficient scaling method called Scaling Information Propagation (SIP) to alleviate the problem of dynamic range growth, which makes full use of bitwidth with much less extra area consumed than the state-of-the-art solutions. In two consecutive transform operations, the SIP method extracts scaling information and makes scaling decisions in the former transform, then executes those in the latter one. We implement the FFT’s VLSI architecture in the orthogonal frequency division multiplexing (OFDM) and the holographic video compression (HVC) systems to verify the SIP method. Compared to the state-of-the-art, experimental results after VLSI synthesis show that our method achieves 9.38% energy reduction and 8.36% area savings when requiring 1.02 × 10-7bit error ratio (BER) of the OFDM system, and 33.47% energy reduction and 30.98% area savings when requiring 20dB signal-to-noise ratio (SNR) of the HVC system, respectively. Fupeng Chen, Raees Kizhakkumkara Muhamad, David Blinder, Dessislava Nikolova, Peter Schelkens, Francky Catthoor, Yajun Ha |
DAC | 3 |