This paper presents the first FPGA accelerator for real-time sort-free 3D Gaussian Splatting. Algorithm–architecture co-optimization is applied by eliminating global depth sorting and adopting a weighted-sum accumulation scheme. The proposed design enables a fully pipelined and hardware-friendly rendering architecture with high parallelism. In addition, a Gaussian pruning strategy reduces the number of Gaussians by 64%–80% with quality degradation less than 1.35 dB. The Width Predictor is designed to eliminates 21.5% redundant pixel computations, while the Diagonal Rendering Mode further reduces latency and achieves 2× area efficiency. A scale-adaptive covariance computation unit ensures stable FP16 computation by mitigating numerical overflow. This work is implemented on a AMD-Xilinx Alveo U200 FPGA, achieving 637.6 FPS at at 600×340 resolution while consuming 2.7 W at a clock frequency of 60 MHz. Compared to prior FPGA-based rendering accelerators, this work achieves 7.64×–12.76× higher energy efficiency, demonstrating an efficient and scalable solution for real-time 3DGS rendering.

Trends in high pin density and an increasing number of routing layers complicate printed circuit board (PCB) routing, which is categorized as escape and area routing. Traditional escape routing research has focused on escape routing but has not considered the quality of area routing among chip components at the same time. In this work, we propose a complete PCB routing methodology, including simultaneous escape routing (SER), post-SER refinement, and gridless area routing. The SER completes the layer assignment of all nets and produces an escape order ensuring suitable escape and area routing on each layer. Length-matching constraints and differential pair routing are satisfied in each stage of the routing flow. The experiment results indicate that the proposed PCB routing method can complete routings for seven commercial PCB designs, whereas the commercial PCB tool cannot complete any of them.