Contemporary semiconductor fabrication nodes present escalating challenges in achieving optimal power-performance-area (PPA) trade-offs, necessitating sophisticated optimization methodologies for digital circuit design. The 2025 ICCAD CAD Contest Problem B [1] introduces significant advances in multibit flip-flop optimization research, establishing a comprehensive benchmarking framework that bridges theoretical algorithm development with practical industrial implementation requirements. This enhanced contest platform, building upon the foundational work of the 2024 iteration [2], delivers unprecedented contributions to the electronic design automation (EDA) research community through mandatory operation traceability protocols, industry-standard LEF/DEF format integration, and enhanced computational resource allocation (16-core processing capability). Our primary research contribution establishes a rigorous validation infrastructure that enables comprehensive algorithmic transparency while addressing real-world optimization challenges encountered in production semiconductor design flows. The framework introduces innovative research enablers including complete transformation audit trails, cross-platform validation compatibility, and systematic performance evaluation under authentic design constraints. Through strategic banking and debanking optimization techniques, research participants engage with fundamental circuit optimization trade-offs while contributing to the advancement of multibit flip-flop optimization science. The enhanced 2025 framework provides the global research community with unprecedented insights into algorithm behavior patterns, transformation correctness verification methodologies, and scalable performance characteristics—essential foundations for advancing state-of-the-art multibit flip-flop optimization research.

In modern designs, timing performance, power, and area constraints (PPA) are the three major metrics for physical design. 2024 ICCAD CAD Contest Problem B investigates the optimization of power, area, and timing in modern semiconductor designs through the strategic use of multibit flip-flops. By banking flip-flops, more area can be freed up, and also efficiently reduce power consumption and reduce net routing complexity. While multibit flip-flop banking has been effective in reducing power and area, it could negatively impact timing performance in critical paths, thus multibit flip-flop debanking could be performed to alleviate timing critical paths. 2024 ICCAD CAD Contest Problem B presents a challenge where participants must optimize the virtual designs by dynamically applying banking and debanking techniques to achieve optimized trade-offs among PPA.

The dramatic growth of hardware attacks and the lack of security-concern solutions in design tools lead to severe security problems in modern IC designs. Although many existing countermeasures provide decent protection against security issues, they still lack the global design view with sufficient security consideration in design time. This paper proposes a security-aware framework against Trojan insertion, frontside probing, and fault injection attacks at the design stage. The framework consists of two major techniques: (1) a large-scale shielding method that effectively covers the exposed areas of assets and (2) a cell-movement-based method to eliminate the empty spaces vulnerable to Trojan insertion. Experimental results show that our framework effectively reduces the vulnerability of these attacks and achieves the best overall score compared with the top-3 teams in the 2022 ACM ISPD Security Closure of Physical Layouts Contest.

Recently, successful applications of reinforcement learning to chip placement have emerged. Pretrained models are necessary to improve efficiency and effectiveness. Currently, the weights of objective metrics (e.g., wirelength, congestion, and timing) are fixed during pretraining. However, fixed-weighed models cannot generate the diversity of placements required for engineers to accommodate changing requirements as they arise. This paper proposes flexible multiple-objective reinforcement learning (MORL) to support objective functions with inference-time variable weights using just a single pretrained model. Our macro placement results show that MORL can generate the Pareto frontier of multiple objectives effectively.

AI-dedicated hardware designs are growing dramatically for various AI applications. These designs often contain highly connected circuit structures, reflecting the complicated structure in neural networks, such as convolutional layers and fully-connected layers. As a result, such dense interconnections incur severe congestion problems in physical design that cannot be solved by conventional placement methods. This paper proposes a novel placement framework for CNN accelerator units, which extracts kernels from the circuit and insert kernel-based regions to guide placement and minimize routing congestion. Experimental results show that our framework effectively reduces global routing congestion without wirelength degradation, significantly outperforming leading commercial tools.