Current microfluidic design automation (MFDA) solutions are limited by the planarity requirements of current manufacturing techniques. Recent advances in stereolithography 3D printing create an opportunity for new MFDA design methodologies. We propose a methodology for the placement of microfluidic components and the routing of flow and control channels in three dimensions. Additionally, we propose a methodology for generating a printable 3D structure from the layout. We then present OpenMFDA, an open-source MFDA design flow implementing the proposed methodologies. This design flow takes a structural netlist and produces a sliced design for manufacturing using an SLA 3D printer. Our methodology demonstrates short run times and generates devices with 2–20 x smaller area compared to state-of-the-art MFDA tools.

Microfluidic devices have emerged as powerful tools in various laboratory applications, but the complexity of their design limits accessibility for many practitioners. While progress has been made in microfluidic design automation (MFDA), a practical and intuitive solution is still needed to connect microfluidic practitioners with MFDA techniques. This work introduces the first practical application of large language models (LLMs) in this context, providing a preliminary demonstration. Building on prior research in hardware description language (HDL) code generation with LLMs, we propose an initial methodology to convert natural language microfluidic device specifications into system-level structural Verilog netlists. We demonstrate the feasibility of our approach by generating structural netlists for practical benchmarks representative of typical microfluidic designs with correct functional flow and an average syntactical accuracy of $\mathbf{8 8} \boldsymbol{\%}$.

Air quality impacts on human health are an increasing concern globally. Vehicle pollution is a particular concern because of its multiple adverse health effects, and discretionary vehicle idling contributes significantly to local-scale poor air quality. This study introduces a novel approach to traditional static (non-changing) anti-idling signage. Here, we demonstrate a system, called SmartAir, that provides dynamic social-norm messages to drivers coupled with information about idling status or vehicle emissions in the area. A machine learning algorithm with audio and video inputs determines vehicle idling status. Vehicle emissions are measured using a suite of low-cost air quality nodes. In this study, we show that the SmartAir system reduces idling time by 28.0% and local CO2concentrations by 29.5% compared to background.

In this paper, we propose a methodology for measuring figures of merit relevant to microfluidics practitioners. We also present a benchmark suite for microfluidics design automation (MFDA). The suite is composed of generated circuits designed to challenge tools for specific figures of merit identified in the measurement methodology. We survey the MFDA literature to evaluate the state-of-the-art for benchmark and measurement methodologies. We include in the benchmark distribution a complete set of transcriptions of the major benchmarks used in the MFDA literature, including designs previously unavailable. Benchmarks are distributed in the major hardware description languages along with reported measurements

We propose a general purpose logic element with eight variations, built using multigate ambipolar transistors, sufficiently capable to replace LUTs in FPGAs. We simulate the new logic element using a 10nm silicon-nanowire three-input-gate transistor model, and compare the proposed element to lookup tables and reconfigurable logic elements from the literature implemented using the same technology model. We compare the different elements for delay, power, and number of transistors, specifically accounting for the cost of configuration storage. Compared to an equivalent LUT, the logic element variation with the most available boolean functions uses 90% of the transistors, with a penalty in delay of 102%, and improved dynamic and static power of 97% and 91%, respectively. The smallest variation uses 42% of the transistors, with improved delay of 76%, and improved dynamic and static power of 43% and 43%, respectively.

Three-Independent-Gate FET (TIGFET) technology is one of the most promising candidates to succeed CMOS and FinFET technologies due to its low off-current, compact surface area, reconfigurable logic, and CMOS compatibility. In this paper, we present an open-source standard cell library based on silicon nano-wire TIGFETs, which enables efficient implementation of novel XOR-and-majority-based circuit designs. We also discuss logic synthesis methods tailored to take advantage of TIGFET capabilities to allow their potential to be realized at the system level. By combining the 10nm TIGFET technology with a mixed logic synthesis tool, the PicoRV core design shows a 2.3× lower area and a 5.7× lower energy consumption, compared to an equivalent low-power 12nm FinFET implementation.

High Level Synthesis (HLS) speeds hardware development and opens the door to non-expert designers, focusing on functionality rather than implementation. The expense and rigidity of commercial electronic design automation (EDA) tool-chains can be an obstacle for these users. LSOracle is an opensource logic synthesis tool which leverages multiple underlying data structures, including and-inverter graphs (AIGs), majority-inverter graphs (MIGs), and xor-and graphs (XAGs) to automatically optimize circuits using the best representation for each region of a design, without manual intervention. The use of MIGs and XAGs gives particularly strong performance in arithmetic logic, cryptography cores, and machine-learning accelerators; applications which may be of particular interest for HLS users. Here we present an overview of the approach and demonstrate an open-source HLS-to-GDS II workflow using LSOracle, Bambu, and OpenROAD. We test the integration on a small benchmark suite and show a reduction in delay of up to 31%.