Considering 3D NAND flash has a new property of process variation (PV) , which causes different raw bit error rates (RBER) among different layers of the flash block. This article builds a mathematical model for estimating the retention errors of flash cells, by considering the factor of layer-to-layer PV in 3D NAND flash memory, as well as the factors of program/erase (P/E) cycle and retention time of data. Then, it proposes classifying the layers of flash block in 3D NAND flash memory into profitable and unprofitable categories, according to the error correction overhead. After understanding the retention error variation of different layers in 3D NAND flash, we design a mechanism of data placement, which maps the write data onto a suitable layer of flash block, according to the data hotness and the error correction overhead of layers, to boost read performance of 3D NAND flash. The experimental results demonstrate that our proposed retention error estimation model can yield a R 2 value of 0.966 on average, verifying the accuracy of the model. Based on the estimated retention error rates of layers, the proposed data placement mechanism can noticeably reduce the read latency by 29.8 % on average, compared with state-of-the-art methods against retention errors for 3D NAND flash memory.

The innovative stacking architecture of 3D NAND flash offers a promising solution to increase the capacity of flash memory and further cut down the per-unit price. Such compact architectures, however, cause varied kinds of errors because of the hardware nature. Specially, retention errors are primary causes of read retries in high-density flash memory, which are induced by charge leakage over time. This paper proposes an empirical mathematical model to estimate the error rate caused by retention errors on the granularity of block, which is the basic program/erase (P/E) unit in 3D NAND flash memory. Specifically, we build the generalized model by considering the factors of layer-to-layer interference, early retention loss, the P/E cycle and the retention time of data of 3D NAND flash memory. Then, we validate the model on four commercial 3D NAND flash products, and the experimental results verify the accuracy of our proposed estimation model. At last, we apply our model in the existing I/O optimization of write scheduling for 3D NAND flash memory, for showing its contributions to better I/O performance.

This article proposes a low I/O intensity-aware scheduling scheme on garbage collection (GC) in SSDs for minimizing the I/O long-tail latency to ensure I/O responsiveness. The basic idea is to assemble partial GC operations by referring to several determinable factors (e.g., I/O characteristics) and dispatch them to be processed together in idle time slots of I/O processing. To this end, it first makes use of Fourier transform to explore the time slots having relative sparse I/O requests for conducting time-consuming GC operations, as the number of affected I/O requests can be limited. After that, it constructs a mathematical model to further figure out the types and quantities of partial GC operations, which are supposed to be dealt with in the explored idle time slots, by taking the factors of I/O intensity, read/write ratio, and the SSD use state into consideration. Through a series of simulation experiments based on several realistic disk traces, we illustrate that the proposed GC scheduling mechanism can noticeably reduce the long-tail latency by between 5.5% and 232.3% at the 99.99th percentile, in contrast to state-of-the-art methods.