The growing interest in autonomous driving technologies requires the creation of efficient real-time systems to understand road scenes. Semantic segmentation, an essential task in computer vision, is crucial in this scenario and has become a viable solution for real-time applications largely due to deep learning models. In terms of hardware for systems with real-time constraints, embedded GPUs are a straightforward solution and provide an easy deployment. At the same time, FPGAs have proven to be more efficient for embedded machine vision tasks, especially in terms of power consumption. However, implementing large and complex models on resource-constrained devices such as FPGA and reaching a high frame rate and a low latency while preserving the semantic segmentation performance is a major challenge, due to the required trade-off between resources and accuracy. Consequently, the choice of model is not straightforward and requires joint consideration of implementation complexity and accuracy on the task. This work aims to demonstrate that, with appropriate training and FPGA-oriented redesign, a low-complexity neural network can match the performance of more complex state-of-the-art networks.

In this study, we propose an implementation methodology of real-time few-shot learning on tiny FPGA SoCs such as the PYNQ-Z1 board with arbitrary fixed-point bit-widths. Tensil-based conventional design environments limited hardware implementations to fixed-point bit-widths of 16 or 32 bits. To address this, we adopt the FINN framework, enabling implementations with arbitrary bit-widths. Several customizations and minor adjustments are made, including: 1.Optimization of Transpose nodes to resolve data format mismatches, 2.Addition of handling for converting the final "reduce mean" operation to Global Average Pooling (GAP). These adjustments allow us to reduce the bit-width while maintaining the same accuracy as the conventional realization, and achieve approximately twice the throughput in evaluations using CIFAR-10 dataset.