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Tresa Joseph

dblp:306/6023 · DBLP profile ↗
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1ranked-venue papers
1as first author
1since 2021 · last 2023
0000-0002-2624-376XORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%
Artificial intelligence
1 paper
Deep learning architectures and training · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
activation function implementation
0.712023
Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
LSTM accelerator
0.712023
Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.712023
Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Machine learning › Deep learning architectures and training › recurrent neural network
LSTM
0.212023
Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Machine learning › Deep learning architectures and training
recurrent neural network
0.212023
Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
YearPublicationVenuePosition
2023 Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions
abstract
This article proposes a new activation function (AF)$\mathrm {sinh}(\beta x) + \mathrm {sinh}^{-1}(\beta x)$called combined hyperbolic Sine (comb-H-sine) to replace existing AFS like$\sigma $and$\tanh $in long short-term memory (LSTM) neural networks. The comb-H-sine function is implemented using purely combinational architectures with a 16-bit data width with fixed-point representation, resulting in improved accuracy. Both software and hardware modeling are used to investigate the proposed architecture. Compared to prior works on$\sigma $and$\tanh $functions, the hardware for the comb-H-sine function shows significant improvements in power consumption, number of cells, cell area, and delay. The proposed LSTM architecture using comb-H-sine outperforms existing AFs in terms of power delay product and accuracy on various datasets.
Tresa Joseph, T. S. Bindiya
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1