Due to the increasing demand for off-chip data transfers, the traditional Von-Neumann architecture faces challenges with modern data-intensive applications, leading to the memory-wall problem. Near-memory processing (NMP) provides a solution by placing computation units near the main memory, which reduces off-chip data transfers and improves system performance. Under this paradigm, some portions of the application are transferred and executed on the NMP side, known as computation offloading. This article introduces a novel computation offloading approach for NMP-enabled 3-D memory systems, considering several critical factors collectively, including data locality information at the last-level cache and execution time estimation of the offloadable portions, which have not been collectively explored in existing studies. Further, this article proposes two different load-balancing strategies to distribute workloads among the NMP cores in the 3-D memory, thereby improving overall performance further. Extensive experiments using a variety of applications from different application domains demonstrate the effectiveness of the proposed approach. Our approach achieves a maximum speedup of$2.34\times $and$1.91\times $compared to traditional and state-of-the-art approaches, respectively. The proposed approach also reduces off-chip data transfers by nearly$5.3\times $compared to traditional computing architectures. Furthermore, the best-proposed approach reduces energy consumption by 26% (maximum) and 21% (average) compared to various state-of-the-art approaches.

The data-intensive applications of today's big data era often produce a large memory footprint. As a result, a significant volume of data needs to travel from memory to the CPU under the traditional Von-Neumann computing paradigm. Near-memory processing (NMP) or processing-in-memory (PIM) is a potential alternate computation framework where a computation unit is placed near the memory (or inside the memory) and a portion of an application is executed on it (termed computation offloading) aiming to reduce the amount of data movement and its consequences. Although a few computation offloading strategies have been proposed in recent times, the existing approaches do not consider the data locality offered by the last level cache and the overall execution time of the application while designing their policies. In this paper, we propose a data locality-aware computation offloading strategy for a hybrid computing system comprising the host processor and NMP-enabled 3D memory. After the application code is instrumented using the LLVM compiler framework, the strategy offloads a portion of an application to NMP if its estimated overall execution time is less. An extensive simulation performed on a set of standard simulators for a bunch of large graph-based application benchmarks reports the effectiveness of the proposed strategy by achieving a maximum speedup of 40% and 11.8% as compared to the host-only configuration and the state-of-art policy, respectively. The proposed strategy also reduces the off-chip data transfer and energy consumption by a significant margin as compared to the host-only configuration (avg 27%) and the state-of-art policy (avg 28%). Further, the proposed policy reduces the LLC miss rate by 57% as compared to the state-of-art policy.