The traditional screening method of using non-layout aware port level fault based scan ATPG tests, traditional toggle patterns, and IDDQ based stress patterns for digital logic has been an industry standard for the last few decades to achieve very low outgoing Defective Parts Per Million (DPPM) integrated circuits in the semiconductor industry. In addition to catching defects that already exhibit catastrophic behavior directly after manufacturing, latent defects need to be accelerated through stress so that they can also be caught before the affected parts are sold. As the FinFET technology process nodes keep shrinking to single digits (especially at 7nm and below), the challenges of creating and measuring transistor level stress patterns for SoC designs increases exponentially. This paper will present the motivation, need, and details of on-going research on Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM generation and targeted scan stress pattern creation to continue achieving zero defect automotive chips in single-digit FinFET process nodes. This new flow enabled quantification of 3 new defect-oriented stress coverage metrics and highlighted the inadequacy of the current toggle coverage metric that overestimates the actual stress coverage achieved.

Cell-neighbor-bridging defects between logic and filler cells were detected on an automotive design after a highly resistive short defect was activated during an internal reliability assessment, having previously passed all wafer probe and package Final Test stresses and screens. The impacted cell’s nodes were confirmed to be stressed and tested as intended at the wafer probe insertion, but not sufficiently enough to activate and observe the effect of the highly resistive defect’s impact on the circuit behavior. The paper discusses a new methodology that identified and located all instantiations of the affected cell combinations in the sea of gates, and development of new stress and test stimuli using User Define Fault Models (UDFM) to target only the affected cell combinations. Limiting the reach of the enhanced stress and test in this way enabled a cost effective and high-quality solution to accelerate activation and improve detectability of the latent defect during silicon test flows.

Achieving zero defects has historically relied on port-level test-coverage (TC) from traditional scan Stuck-At and Transition-Delay tests. Defect-Oriented tests from Siemens showed a way detecting more defects and to measure test coverage using layout-based Total Critical Area. With the ever-shrinking process nodes, the BEOL layers are closer together and the redundancy factor of vias, especially the lower VIA layers has been dropping down significantly. Internal studies from quality and reliability failures confirmed non-redundant (NR) VIA defects that escaped all traditional detailed test coverage analysis. This motivated us to develop a new industry first per-layer NR VIA fault model extraction flow, which enabled us to successfully quantify NR VIA TC for sets of scan ATPG tests running in production test program. Details of a case study using new fault extraction and fault simulation flow to quantify per-layer NR VIA TC will be discussed in this paper.

Continuous analysis of multiple defective dies on a FinFET design indicated a failure mechanism with resistive defect on one library cell. All the units under study had passed the wafer probe test flow and only failed during internal quality and reliability study flows. In this paper, we present the details of developing and deploying targeted stress and test patterns using custom hand-written User Defined Fault Model (UDFM) files. This was essential to address a failure mechanism that was root-caused to not enough high-voltage stress applied in order to accelerate the resistive defect in wafer probe test flow. The defect location inside this cell created feedback in the circuit that limited the current through the defective path, making it more difficult to both accelerate and detect the existence of the problem in wafer probe test flow. A novel solution using the combination of targeted custom ATPG patterns to stress and accelerate the defect mechanism and custom ATPG patterns to also screen defects were generated using the custom UDFM file and deployed in the wafer probe test flow. Finally, we will present unique silicon fallout data from the targeted custom tests which confirmed effectiveness of targeted stress to accelerate and screen defective die early in wafer probe test flow.

After a continued analysis of more than a year to reduce DPPB on NXP automotive designs, it was observed that some subtle at-speed defects were not getting screened out using combination of traditional Stuck-At, Transition-Delay and Small-Delay-Defect based ATPG patterns. Traditional delay fault models for automatic test pattern generation target a single transition that propagates to the output(s) of a gate. Single Transition-Delay model finds the stimulus that can sensitize a transition on a port that, in presence of a delay defect, will result in the capture of incorrect state. Failure Analysis data confirmed that multiple transitions on inputs changed the timing of the outputs in a different way than a single transition, in the presence of subtle defect mechanisms in certain library cells. Multiple Input Switching (MIS) is a known STA modeling problem that can affect the timing of a gate under various conditions of load, slew, and temporal distance of signals at the inputs. In this paper, we present a new ATPG fault model that complements the traditional transition delay models and, a method to identify the stimuli required to expose these kinds of defects. The new patterns were first validated on the tester, resulting in proof of concept of new methodology. Later, at-speed Multi-Transition Fault Model (MTFM) ATPG patterns were released for multiple NXP AUTO designs and high-volume yield data from more than 9 million units confirmed unique fallout of at least 0.5ppm from the new MTFM topoff patterns. Also, MTFM based input stimuli comparison was done on limited set of library cells between MTFM and traditional Cell-Aware 2 Time-Frame UDFM based patterns. It was confirmed that only MTFM patterns produced the required multi-transitions through the inputs of the targeted cell instances in multiple designs.