There are several applications of functional simulation with transient faults including evaluation of the vulnerability and design error-tolerant measures, as well as debugging of electrical hardware issues. Yet, the simulation is extremely slow given the complexity of RTL circuits and a large number of transient faults proportional to the total execution cycles. Recently, fault reduction methods are developed with Architecturally Correct Execution (ACE) analysis. The method can identify only about 3 % of total faults deemed necessary for simulation. However, the analysis effort is still non-trivial and most of the time is consumed in the small single-cycle fault simulation. In this paper, we proposed to use FPGA emulation to speedup the above process. In the experiments, on a RISC- V core, for a set of 16K faults, the analysis time are reduced from 1 hours to 1min, On average, the fault emulation has a speed up factor of 60 compared with a software implementation.

To satisfy requirements of system reliability, the importance of debugging grows increasingly to identify functional errors of SoC caused by transient faults. Yet, due to the complexity of a SoC, efforts to locate faulty signals and cycles are also dominating the yield ramp up period. Debugging-assisted circuits and associated tools play an essential role to keep the costs down. Notably, QED [1] and EQED [2] methods can use observation points, hardware checkers, and MISR to limit the candidate faulty cycle range and to prove the faulty signal candidates through bounded model checking (BMC). In this paper, we proposed a transient fault list reduction method as a filter before we apply BMC to check the validity of faulty signals and cycles. The method identifies the propagation condition of faults and constructs a set of fault traces (a tree of equivalent propagated faults) to examine and classify the transient faults. The roots found in the fault traces can significantly reduce possible faulty candidates to check with BMC. In our experiments of a RISC-V core, we can reduce the time spent on BMC from 97 hours to 6 hours of simulation and graph analysis on average. Overall, we can reduce the initial faulty candidates to under 5% or less of original list.

It is essential to perform extensive RTL functional fault simulation for critical systems in order to analyze the vulnerability and design error-tolerant measures accordingly. Since the number of faults would be exceedingly large for a full simulation, fault sampling techniques are applied. However, little information are available for fault characteristics, so the sampling might not be effective: often producing no error output or similar output syndromes.In this paper, we utilized an advanced Architecturally Correct Execution (ACE) analysis to study the functional fault characteristics of registers on a RISC-V core. From the results for all registers, only less than 0.34% to 2.76% of total faults need to be simulated. We then further sample and simulate these remained faults at RTL to analyze the categories for failure output syndromes. We found that faults at non-architecture registers have much higher masked results (as high as 90%), as compared with architecture registers (16% – 40%). Therefore, it is suggested that fault sampling should consider register and fault characteristics for a more effective result.

Critical systems require extensive simulation effort with functional fault injection on RTL circuits during design stages in order to analyze vulnerability and engineer error-tolerant measures accordingly. Yet for a complex SoC, long simulation cycles are necessary for each injected fault. Therefore it is imperative to prune as many faults as possible to improve simulation efficiency and turn-around time for designers.In this paper, we propose a novel method (ACE-Pro) to reduce the functional fault list. The method extends architecturally correct execution (ACE) analysis by creating a propagation graph, where a node is a fault marked with an ACE bit at a cycle and a directed link between nodes represents the propagation condition to another register at the next cycle. By checking and propagating through the graph the properties of masking (a fault is masked by logic on its propagation path to next registers) and singly-equivalence (a fault is covered by another fault on the next register), we show fault reductions by 98.91% to 99.91% (49.2% to 88.4% from the reduced faults in Equivalent Regions) in our experiments on a RISC-V core.