This paper presents a$2\times 80$Gb/s single-ended trans-admittance trans-impedance (TAS-TIS) 4-level pulse amplitude modulation (PAM-4) receiver with crosstalk cancellation and signal reutilization technique in 28-nm CMOS. Based on the TAS-TIS architecture, to achieve a precise cancellation of the far-end crosstalk, a common mode gain rejection methodology is proposed in the balanced differentiator, ensuring low gain mismatch and low phase skew. Moreover, the proposed Gm-doubler technique in the TAS-TIS architecture enhances the gain of the adder under limited supply voltage conditions. By employing the series peaking combined with an active inductor in the adder, the bandwidth of adder is improved by a factor of 2.2, and the group delay variation is effectively optimized by 65%. The proposed current-mirror-based continuous-time linear equalizer (CTLE) provides high-frequency and low-frequency compensation with 25% power saving. Overall, the measurement results of the proposed receiver demonstrate$2\times 80$Gb/s PAM-4 eyes with an efficiency of 0.83 pJ/bit/lane and$2\times 56$Gb/s non-return-to zero (NRZ) eyes over a pair of PCB traces with 13 dB loss at 20 GHz and 28 dB loss at 28 GHz, respectively.

A tri-mode mixer supporting the 5G NR standards over 24.25--71GHz is presented. The harmonic-selection technique reduces the local oscillator (LO) frequency range and power consumption. Besides, the proposed multiphase LO rejects unwanted harmonics. Fabricated in a 65nm CMOS process, this work consumes 12-21mW power under a 1V supply. It presents more than 20dB rejections to the undesired harmonic components at all operation bands. The required LO frequency range is only 10GHz.

An 8-Element 28-GHz time-division MIMO beamformer supporting 4x4 MIMO is presented. A fast-switching phase shifter is utilized to realize Nyquist-rate beam switching to lossless receive multiple beams by reuse single RF signal path. A prototype fabricated in 65nm CMOS achieves 64-QAM 4x4 MIMO reception in OTA measurement using four 5G NR spatial data streams with 400MHz channel bandwidth.

This paper presents a tri-mode band-selection CMOS down-conversion mixer supporting the 5G NR standards over 24.25–71 GHz. The harmonic-selection technique reduces the required local oscillator (LO) frequency range and power consumption. The second-harmonic selection mode works for the 39-GHz and 47-GHz bands, while the fundamental-selected and third-harmonic selection modes operate for the 28-GHz and 60-GHz bands, respectively. Besides, in cooperation with the proposed multi-phase LO, the mixing components behave destructively for the undesired harmonics and constructively for the desired component, which shows the rejection of unwanted harmonics. Fabricated in a 65-nm CMOS process, this work presents flat conversion gain and more than 20-dB rejections to the undesired harmonic components at all operation bands. The required LO frequency range is only 10 GHz. Occupying a core area of 0.0077 mm2, the proposed mixer consumes power of 12-21 mW in three modes under a 1-V supply.

This paper presents a fully-integrated flipped-voltage-follower-based low-dropout regulator (LDO), with proposed high-gain two-stage cross-coupled error amplifier (XCEA). Besides, the effectiveness of bypass capacitors and diversified load capacitors is discussed. Consuming$\mathbf{170}-\boldsymbol{\mu} \mathbf{A}$quiescent current and occupying area of 0.019 mm2, the LDO features 25-MHz unity-gain bandwidth (UGB) at 20-mA load to satisfy fast response requirement in high-speed transmitter. The simulated voltage undershoot is 38.85 mV for a load transient current stepping from$\mathbf{1}\ \boldsymbol{\mu} \mathbf{A}$to 25 mA in 50 ps with$\boldsymbol{C}_{\mathbf{L}} =\mathbf{100}\ \mathbf{pF}$. Owing to the proposed XCEA and the filter capacitor, the PSR is measured to be -41 dB at 100 kHz and -36 dB at 1 MHz.