To achieve high test coverage for scaled-down high-speed memory, the hardware complexity of the algorithmic pattern generator (ALPG) in automatic test equipment (ATE) has increased due to the demands of high-speed operation. However, the potential for further speed-up is constrained by the challenges associated with pipeline insertion and signal integrity preservation. Unlike ALPGs, test patterns in vector memory (VM) are generated by simply fetching pre-stored patterns without performing complex operations. Although its fetching logic is advantageous in high-speed operation, the speed of VM-based pattern generation is limited by the VM load speed. Furthermore, the limited VM capacity restricts the storage of extensive test patterns. To address the limitations of both approaches, a vector memory using bit-level address segmentation (VASE) that enables high-speed memory testing is proposed. VASE improves pattern generation speed by cyclically reusing test patterns while reducing the required VM capacity. Although VASE may impose some limitations on test algorithm coverage and incur overhead in logic area and power consumption, it still supports a wide range of commonly used test algorithms. Considering the speed improvements achieved, these trade-offs are acceptable for ATE applications.

Chiplet-based systems provide a scalable platform for heterogeneous integration, but permanent faults in interconnects and memory cells challenge their reliability. While standards like Universal Chiplet Interconnect Express (UCIe) employ single-domain system Error Correction Code (ECC) simplify architecture, they often limit fault isolation and recovery. This paper proposes a dual-mode Online Built-In Self-Repair (OBISR) architecture for unified detection and repair of both interconnect and memory faults during post-bond testing and in-field operation. Unlike conventional methods that merely expand ECC capacity, the OBISR targets the root causes of persistent errors by repurposing existing Content-Addressable Memory (CAM) and pathfinding logic. A hierarchical CAM structure classifies faults using spatial and recurrence patterns of ECC metadata to distinguish permanent defects from transients. Memory faults are masked via logical redirection, while interconnect faults are rerouted, both operating outside the datapath to ensure zero performance degradation. Evaluations demonstrate that the OBISR improves system-level resilience by 235.49% and reduces hardware area by 16.69% compared to conventional schemes. Its integrated dual-domain and dual-mode capabilities offer a robust, scalable solution for next-generation chiplet reliability.

To reduce the cost of memory production, built-off self-test (BOST) enables low-speed automatic test equipment to test the high-speed memory. To maximize the cost reduction benefit of BOST, it is crucial to test as many memories as possible using as few test output pins as possible. For this purpose, a new pipelined output data reducer called PODR is proposed for the output data reduction, and channel sharing between memories tested in parallel is introduced. The proposed structure is adopted to reduce hardware complexity while facilitating test output channel sharing between concurrently tested memories. Additionally, further output data reduction can be achieved by integrating the output data code into the pipelined structure. Output data reduction is also attainable by transmitting fault cell addresses using relative distance from the previously detected fault cells rather than the absolute addresses. Reducing the total code length can be achieved by the adoption of relative addressing, but this requires additional code transmission as its overhead. To mitigate this overhead, a revised approach to relative addressing is introduced. Consequently, as the number of memories tested in parallel increases, the amount of output data of PODR decreases and the number of normalized test output pins usages is reduced in half compared to the previous works.

An algorithmic pattern generator (ALPG) has been developed within automatic test equipment (ATE) due to the extensive number of test patterns required for testing the memories. Since shared-resource ALPG generates the test pattern using the same arithmetic instruction and timing across multiple input/output (I/O) pins, the maximum operating frequency is limited by the delay of the arithmetic operation. On the other hand, per-pin ALPG can achieve high-speed operations by generating one bit of the test pattern for each I/O pin. However, the hardware cost is significantly increased due to the need for individual instruction and pattern generator (PG) for each I/O pin. To address these limitations, a cost-effective per-pin ALPG for high-speed memory testing is proposed. The proposed per-pin ALPG can achieve high-speed operations, and the hardware resources for storing and decoding the instructions are shared among multiple I/O pins to reduce the hardware cost. The experimental results indicate that the proposed ALPG can achieve a higher speed than the conventional per-pin ALPG with a reasonable hardware cost comparable to the conventional shared-resource ALPG.

Memory test and repair has been generally applied to improve memory yield. However, due to the high cost of automatic test equipment (ATE) equipment, which has been employed for memory test and repair, there is a significant focus on reducing the ATE expense. One of the major problems, which contribute to the increase in ATE cost, is fail address memory. The size of fail address memory, where memory fault information is stored during the memory test, has continuously grown in line with the memory capacity increase. To address the problem, a new fail address memory architecture for cost-effective ATE is proposed in this article. In the proposed architecture, memory fault information is compressed and unrequired memory fault information is eliminated. In addition, a new structure of fail address memory is used to efficiently store memory fault information. Accordingly, the size of fail address memory is highly reduced in the proposed architecture. Furthermore, since some information, which can be used during the memory repair, can be collected during the memory test, the redundancy analysis time required to find memory repair solutions is also reduced in the proposed architecture. The advantages were verified experimentally.

As fault occurrence probability has increased with corresponding increases in memory density and capacity, memory test and repair have been widely used. However, the total cost for these has increased dramatically due to the increased cost of automatic test equipment (ATE) and the time required for redundancy analysis (RA). The increase in ATE cost has been caused by the increased size of fail address memory, where memory fault information is stored during memory test. The RA time has also increased because the difficulty encountered during fault analysis has increased in proportion to the increase in the number of memory faults. To address these problems, an RA-aware fail data collection architecture is proposed. This includes a new fail address memory structure that can significantly reduce the fail address memory size. Moreover, the architecture can integrate memory fault information using simple calculations without any data losses. In addition, unnecessary memory fault information can be eliminated easily with efficient data encoding to reduce the data size. Furthermore, since some information required for fault analysis in memory repair can be collected during memory test, the RA time needed to find memory repair solutions is also reduced without any degradation in the repair rate. Consequently, the total cost for memory test and repair can be considerably reduced by reducing the cost of ATE and the RA time. Experimental results reveal that the fail address memory size and RA time can be reduced by an average of 63% and 41%, respectively, with the proposed architecture.

A voltage-divider-based through-silicon-via (TSV) test architecture tests the TSV by using the voltage value differently divided according to TSV defects. This architecture is widely used for TSV testing owing to its small hardware overhead and high test speed. However, the existing voltage-divider-based TSV test architectures are vulnerable to process–voltage–temperature (PVT) variations and noise. In addition, they cannot effectively detect pinhole defects. This study proposes a novel error-tolerant voltage-divider-based TSV test architecture to address these problems. The proposed architecture reduces the test errors by appropriately adjusting the on-resistance value of each MOSFET and adding a compensator circuit. In addition, it effectively detects the pinhole defects by modifying the voltage divider structure and changing the MOSFET control method. Experimental results reveal that the proposed architecture promptly tests various TSV defects and significantly reduces the test errors.