Demo Data from EDBT 2026 / reviewers in the wild / expert
Gaeryun Sung
dblp:308/0190
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2025
0000-0002-7932-650XORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 87% Integrated circuit design · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
layout synthesis |
0.7 | 1 | 2023 | LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Electronic design automation
physical design |
0.7 | 1 | 2023 | LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Integrated circuit design › semiconductor device fabrication
CMOS technology |
0.2 | 1 | 2023 | LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Methods — techniques the papers use, named apart from their topics
parasitic extraction · 0.7dynamic template generation · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | A Variation-Robust 20-Gb/s Wireline Transceiver With Real-Time Calibration in 28-nm CMOSabstractThis paper describes a variation-robust transceiver with four-tap feed-forward equalization (FFE) and real-time calibration techniques. The design adopts the common-mode balanced and robust FFE (CMBB-FFE), which improves the previous current-mode coefficient-error-robust FFE (B-FFE) to achieve the consistent common-mode level across data patterns and support voltage mode operation. The real-time receiver calibration method adjusts sampling threshold voltages and clock phases in the middle of normal link operation, to enhance the sampling margin under dynamic drifting conditions. The transceiver test chip is fabricated in a 28-nm CMOS process. It occupies 0.419 mm$^{\mathbf {2}}$, achieving 20 Gb/s with 9.82-pJ /bit energy efficiency and 33.3% wider horizontal eye-opening by adopting the CMBB-FFE and real-time calibration techniques. Sangwan Lee, Hyeongmin Seo, Wookjin Shin, Dongju Yang, Gaeryun Sung, Dong-Ho Choi, Young-Ho Kwak, Soon-Jae Won, Ickhyun Song, Jaeduk Han |
IEEE Trans. Circuits Syst. I Regul. Pap. | 5 |
| 2023 | LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS TechnologiesabstractThis article presents an automatic layout generation framework in advanced CMOS technologies. The framework extends the template-and-grid-based layout generation methodology to produce optimal layouts more efficiently. Layout templates and grids are dynamically created and adjusted during the generation phase to provide more reusability and flexibility. Virtual instances are used to encapsulate the dynamically generated layout structures. Internal node probes embedded in the dynamic templates capture parasitic effects precisely. The framework also implements various post-processing functions to handle process-specific tasks while maintaining the overall process portability of procedural layout generators. The post-processing functions include cut/dummy pattern generation and multiple-patterning adjustment. The generator description coverage is enhanced with circular grid indexing/slicing and conditional conversion operators. The layout generation framework is applied to generate various DRC/LVS clean layouts automatically in advanced CMOS technologies, achieving 0.66–249.35 transistors-per-line (the ratio of the generated transistor count to the source lines of code) generation efficiencies. Taeho Shin, Dongwhee Kim, Gaeryun Sung, Wookjin Shin, Yunseong Jo, Hyungjoo Park, Jaeduk Han |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |