EDBT 2026 Demo / reviewers in the wild / expert
Kyungjoon Chang
dblp:308/0317
· DBLP profile ↗
3ranked-venue papers
2as first author
3since 2021 · last 2024
0009-0002-3693-7738ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.8 | 1 | 2024 | DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Electronic design automation › physical design
placement and routing |
0.8 | 1 | 2024 | DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Electronic design automation › timing prediction
pre-routing timing prediction |
0.8 | 1 | 2024 | DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Electronic design automation › physical design
timing optimization |
0.8 | 1 | 2024 | DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Methods — techniques the papers use, named apart from their topics
deep learning · 0.8continual learning · 0.8anomaly detection · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Pre-route timing prediction and optimization with graph neural network models
Kyungjoon Chang, Taewhan Kim 0001 |
Integr. | 1 |
| 2024 | DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality EnhancementabstractDeep learning (DL) models have recently paid considerable attention to timing prediction in the place-and-route (P&R) flow. As yet, the DL-based prior works are confined to timing prediction at the time-consuming routing stage, and very few have addressed the timing prediction problem at the placement, i.e., at the pre-route stage. Moreover, no work has addressed a seamless link of timing prediction at the pre-route stage to the final timing optimization through commercial P&R tools. In this work, we introduce a novel framework called DTOC-P that seamlessly integrates deep-learning-driven timing optimization into cutting-edge commercial P&R tools. Our framework is composed of two phases: (1) the pre-route timing prediction phase that performs DL-driven arc delay and arc output slew prediction with an elaborated hierarchical model; (2) the timing optimization phase which incorporates commercial P&R tools with DL-driven prediction outcomes to perform timing optimization. In addition, DTOC-P framework achieves enhanced practicality with the application of continual learning in the timing prediction phase, and the concept of anomaly detection in the timing optimization phase. Experimental results show that our DTOC-P framework improves pre-route prediction accuracy by up to 55% and 47% on arc delay and arc output, which are further enhanced to encompass a broader range of designs by continual learning supported in DTOC-P, practically using a tenfold reduced training time compared to re-training all datasets from scratch. In terms of timing optimization, our experiments reveal that DTOC-P framework improves WNS, TNS, and the number of timing violation paths by up to 12%, 41%, and 34%, respectively, which is a remarkable progress compared to its predecessor through the integration of anomaly detection that excludes potential outliers to effectively protects against erroneous timing updates during the timing optimization phase. Jaehoon Ahn, Kyungjoon Chang, Kyumyung Choi, Taewhan Kim 0001, Heechun Park |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2023 | DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA toolabstractRecently, deep-learning (DL) models have paid a considerable attention to timing prediction in the placement and routing (P&R) flow. As yet, the DL-based prior works are confined to timing prediction at the time-consuming global routing stage, and very few have addressed the timing prediction problem at the placement, i.e., at the pre-route stage. This is because it is not easy to “accurately” predict various timing parameters at the pre-route stage. Moreover, no work has addressed a seamless link of timing prediction at the pre-route stage to the final timing optimization through making use of commercial P&R tools. In this work, we propose a framework called DTOC, to be used at the pre-route stage for this end. Precisely, the framework is composed of two models: (1) a DL-driven arc delay and arc output slew prediction model, performing in two levels: (level-1) predicting net resistance (R), net capacitance (C), and arc length (Len), followed by (level-2) predicting arc delay and arc output slew from the R/C/Len prediction obtained in (level-1); (2) a timing optimization model, which uses the inference outcomes in our DL-driven prediction model to enable the commercial P&R tools to calculate the full path delays, setting update timing margins on paths, so that the P&R tools should use more accurate margins on timing optimization. Experimental results show that, by using our DTOC framework during timing optimization in P&R, we improve the pre-route prediction accuracy on arc delay and arc output slew by 20~26% on average, and improve the WNS, TNS, and the number of timing violation paths by 50~63 % on average. Kyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim 0001 |
DATE | 1 |