Processing-in-memory (PIM) architectures alleviate memory bottlenecks and improve latency and energy efficiency for AI and ML workloads by accelerating general matrix-vector multiplication (GEMV) operations in DNNs. However, permanent faults in arithmetic units (AUs) within processing units (PUs) critically impact yield and inference accuracy. Although the hybrid built-in self-test (HBIST) method has been proposed, it has limited capabilities in diagnosing and repairing faulty AUs within PUs. In this study, a novel Self-Test And Repair structure for PIM (STAR-PIM) is proposed to enable both fault diagnosis and repair by incorporating a bypass mechanism. A scan-path-like approach enables the testing and precise localization of faulty AUs, while faulty adders are bypassed using a redundant adder structure integrated within the memory die. Furthermore, faulty multipliers are masked using the weight-swapping logic. Experimental results demonstrate that STAR-PIM achieves high AU-level test coverage, ranging from 98.89% to 100% with reasonable area overhead. Recovery experiments show that STAR-PIM maintains low relative errors under fault rates up to 1% for GPT-2 and preserves inference accuracy under fault rates up to 3% for MNIST-MLP. Power measurements on GDDR6-AiM indicate an average overhead of 7.39% with only a 0.08% latency increase. Consequently, STAR-PIM significantly enhances the yield and reliability of PIM while reducing test costs, making it a highly practical solution.

In dynamic random-access memory (DRAM), memory redundancy analysis (RA) is a crucial process for enhancing memory yield and reducing production costs. It finds a memory repair solution by efficiently allocating the limited number of spare cell lines that replace a faulty cell. However, it is challenging to quickly find a memory repair solution because RA is an NP-complete problem. To address this issue more effectively, we present a powerful early termination-based high-speed RA method. This method rapidly assesses memory repairability, terminating the RA process early in cases where repair is impossible, or a solution can be easily found. Additionally, by dividing faulty cells into several groups, the proposed RA method finds fast and approximate albeit nonoptimal solution sets for each group. This facilitates the rapid acquisition of a memory repair solution without the need to search for all the optimal solution sets. These features enable RA to be promptly executed while ensuring the repair solution for any repairable memory. Experimental results demonstrate that the proposed RA method can find a repair solution faster than the existing RA methods.

To address the demand for memory scaling capabilities, 3-D integrated circuits (3D-ICs) based on short and dense through-silicon vias (TSVs) have been introduced. However, the defects of TSVs considerably influence the yield and reliability of 3D-ICs. For this reason, TSV repair using switch matrix (SM) topology (TRUST) is proposed in this article. TRUST adopts an SM, which has a high routing flexibility, to realize TSV connections. Consequently, a 100% repair rate can be achieved for the 3D-ICs that have faulty TSVs smaller than or equal to redundant TSVs. Furthermore, TRUST utilizes content-addressable memories in built-in self-repair to identify TSV repair paths via a simple TSV repair path search algorithm. For this reason, TRUST can be applied to repair manufacturing and aging defects of TSVs. Nevertheless, TRUST can be applied with reasonable area and delay overheads, such as 58.3% area reduction and 55.1% delay reduction compared to the only conventional TSV repair architecture that can achieve the optimal repair rate. In addition, the area ratios in high bandwidth memory (HBM) and HBM2 are only 5.3% and much smaller than 0.1%, respectively. The advantages are experimentally verified.

Advances in the density and capacity of dynamic random access memories (DRAMs) have resulted in emerging reliability issues. The error correction code (ECC) is widely used as a promising technique to improve the reliability of high-density memories. For this reason, many studies on ECC have been conducted to address the increased cell failure rates. However, conventional ECCs have shown limited achievements owing to area, latency, and power overheads. This study proposes ECC architecture reusing content-addressable memories (CAMs) for obtaining high reliability in DRAM, which can be called ECMO. The proposed architecture reuses CAMs in built-in self-repair, which can be used to repair memory hard faults during manufacturing as data storage to replace error data words. This achieves high reliability along with an additional 9155 h DRAM lifetime. Nevertheless, it can be implemented with a 3.04% area overhead due to the reuse of CAMs. Moreover, only 0.21 ns is added to the critical path. Furthermore, the power overhead is 0.1% compared to the total power consumption of DDR3 and DDR4.