We demonstrate the simulation of noise- dependent point cloud processing using a compact model of non-volatile memories (NVMs). We investigate how classification accuracy is affected by programming variations in NVMs, representing circuit noise, and distortions in point clouds, representing sensor noise. We employ a PointNet-based framework and explore how the inherent weight-sharing properties of PointNet can leverage NVM crossbars for energy-efficient processing. By benchmarking the performance of both NVM-based PointNet across various noise levels, we demonstrate the impact of different noise types on classification accuracy. Our findings show that while certain circuit and sensor noise degrade classification performance, our NVM-based PointNet achieves competitive results with reduced trainable parameters, providing a path toward neuromorphic 3D vision and computing with co-optimization of software and hardware. Our work highlights the potential for using NVM crossbars to efficiently handle noise-dependent processing in edge inference units.

FFT is utilized in a wide range of spectrum analysis applications. As the data volume dramatically increases in multi-sensor or wideband RF systems, advances in FFT acceleration are required to realize a high-performance back-end digital signal processing unit. A million-point FFT accelerator that is feasible for a single-chip solution is introduced here using an in-memory technique in a NAND flash memory. The million-point FFT accelerator is developed using a compact SONOS NAND flash model with a Gaussian noise distribution. With a 1-bit memory depth, SQNR reaches approximately 110dB. It is comparable to conventional accelerators using FPGAs with a 20-bit twiddle factor and 32-bit output word length, which will be references for the realization of a single-chip solution.

Analog computing platforms have been a popular and promising research area that suggest efficient ways of computation compared to its digital counterparts. Memristor based crossbars drew attention by computing the vector-matrix calculation intensive tasks such as Artificial Intelligence (AI) and Machine Learning (ML) in one time step. Although they provide an energy efficient way of computing these tasks, analog computation in general suffers from non-idealities and systematic errors in the circuitry, which could degrade the performance and accuracy significantly. One of the issues is the random offset associated with the op-amps in the system resulting from the process and mismatch variations. In this paper, a novel technique is offered to reduce the negative effects of the random offset and increase the output accuracy. This newly proposed system uses minimum extra circuitry and additional power consumption and only requires the crossbar to be enlarged by two extra rows. The intrinsic issue of the analog crossbars, interconnect parasitics, must be incorporated into the problem, and a way to separate the offset and wire resistance issues from each other is offered. The functionality of the system has been shown with a case study in the results section where the op-amps have$\sigma_{offset}=3mV$. The effectiveness of the offered technique demonstrates a 6× better accuracy with the mitigation of the offset problem. The proposed method can be used in memristor and other analog crossbars to achieve a greater performance and thus improve their competitiveness.

Over the last decade, Gaussian processes (GPs) have become popular in the area of machine learning and data analysis for their flexibility and robustness. Despite their attractive formulation, practical use in large-scale problems remains out of reach due to computational complexity. Existing direct computational methods for manipulations involving large-scale$n\times n$covariance matrices require$O(n^{3})$calculations. In this work, we present the design and evaluation of a simulated computing platform for exact GP inference, that achieves true model parallelism using memristive crossbars. To achieve a one-shot solution, a linear equation solver and a vector-matrix multiplication solver crossbar configurations are used together, reducing the number of operations from$O(n^{3})$to$O(n)$. The transistor level op-amps, ADC models for quantization, circuit and interconnect parasitics, together with the finite memristor precision are incorporated into the system simulation. The analog system resulted in %1.51 mean error and %2.93 average variance error in solving a nonlinear regression problem. The proposed method achieved 9× to 144× better energy efficiency compared to TPU and 7× compared to a custom analog linear regression solver.

We demonstrate via simulations that transient perturbations introduced by non-zero diagonal elements in a Hopfield network can improve NP-hard graph optimization efficiency by more than a factor of two. Such perturbations enhance the known effects of circuit noise typical of memristor-based networks in escaping local minima (incorrect solutions) and finding the global minimum (correct solution) of the Hopfield energy. We provide systematic simulations of NP-hard graph problems with controlled nonidealities in memristor arrays modeled as noise amplitude and diagonal perturbations. Furthermore, our approach improves Hopfield network optimization efficiencies to solve NP-hard problems regardless of the graph size (30 × 30, 60 × 60, and 80 × 80) and connectivity (30%, 50%, and 70%).

We illustrate novel optimization techniques via simulations for Hopfield networks constructed from manufacturable three-terminal Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) synaptic circuit elements. We first present a computationally-light, memristor-based, highly accurate static compact model for the SONOS synapses used in our simulations. We then show how to exploit analog errors in programming resistances and current leakage, and the continuous tunability of the SONOS synapses to enable transient chaotic group dynamics, to accelerate the convergence of a Hopfield network. We project improvements in energy consumption and time to solution relative to existing CPUs and GPUs by at least 4 orders of magnitude, and also exceed the projected performance of two-terminal memristor-based crossbars in addition to a 100-fold increase in error-resilient array size (i.e. problem size).