Physical unclonable functions (PUFs) are increasingly recognized as a key technology for enhancing hardware and the Internet of Things (IoT) security. The IoT devices are often plagued by weak security measures, making them susceptible to various external threats. To address these vulnerabilities, robust and reliable security solutions are critical. This study introduces a highly reliable and low-power PUF application-specific integrated circuit (ASIC) design specifically designed for the IoT security applications. Initially, the proposed design is deployed on a Xilinx ZYNQ 7000 field-programmable gate array (FPGA) board operating at 100 MHz and later designed and fabricated using the Cadence Innovus in the 180-nm CMOS process on silicon. This work presents and evaluates a novelxnor–xorring oscillator (RO) PUF with a configurable frequency. The design’s performance is analyzed using statistical metrics, including reliability, uniqueness, and uniformity. Thexnor–xorRO PUF ASIC demonstrates max reliability of 91.92%, a uniqueness of 49.62%, and a uniformity of 50.19% on silicon.

Recent digital pulsewidth modulation (DPWM) researches use multiple clock inputs and long D flip-flop (DFF) arrays, which makes scaling to different DPWM frequencies challenging. This brief demonstrates a DPWM that utilizes a single clock and a Matrix shift array, allowing it to be scaled to any frequency and reducing the effects of clock skew. It has a clock gating technique that selects a specific row of DFFs based on the required % duty cycle. The DPWM design has a dead time generator to prevent shoot-throughs. The DPWM has been fabricated using UMC 180-nm CMOS process. The performance and functionality of the DPWM have been verified through the measured comparisons of % duty ratio, dead time ($T_{dt}$), and output frequency ($f_{\text {out}}$) at input clock frequency ($f_{\text {clk}_{\text {in}}}$) equal to 10$\sim $100 MHz. The DPWM design has a maximum % duty ratio of 90.6%,$T_{dt}$= 1.8 ns, and$f_{\text {out}}$= 6.25 MHz with 3.4-mW power consumption at$f_{\text {clk}_{\text {in}}}$= 100 MHz.

This investigation presents a digital logic accelerator (DLA) design of a neural network hardware that utilizes output reuse. The DLA is used in the detection mechanism of underwater objects that was deployed in an underwater vehicle. A modified YoloV3-tiny network was also implemented to detect more than 20 underwater objects. The proposed DLA uses processing units that have parallel architectures of output windows, and output channels. Moreover, a new Inter-Controller is designed to control the direct memory access (DMA) together with a new Reshape module to improve the performance and power efficiency. A detailed description of the design as well as the measurements on silicon are presented. The chip is realized using a typical 180-nm CMOS process. It showed a performance result of 40.96 GOPS and the power consumption is 196.8 mW. The DLA was tested to demonstrate 19.88 frames per second and 40.96 GOPS.