Most digital transformer designs used non-overlapping coil topology, which increases the design area on silicon. This study demonstrates a digital transformer based on a multi-layer, over-lapping coil topology that increases the trans-former’s mutual inductance. Two interwound coils composed of 6 metal layers are implemented to realize the transformer and fabricated using 18 µm HV CMOS process. To demonstrate the operation of the proposed transformer, the rise time (trise), fall time (tfall), and propagation delay (tpro_delay) of six chips are measured at an operating frequency of 10 MHz with a worst power consumption of 52 mW. The digital transformer is also tested at various duty cycles to ensure its suitability for power conversion applications.

This work presents a high-resolution programmable frequency divider to select the frequencies that will be generated in DCO (Digitally Controlled Oscillator) or VCO (Voltage Controlled Oscillator) that will benefit the design of high-speed, wide-range PLL for Internet-of-Things (IoT) applications. The design is verified through post-layout simulations at 1 GHz input clock. The design achieves a division ratio range of 2-2048 with minimum and maximum operating frequencies of 488 KHz and 500 MHz, respectively. This work is carried out using 40-nm CMOS technology at 60 pF capacitive load and an average power consumption in worst case post layout simulation is 0.470 mW at 500 MHz.

Recent digital pulsewidth modulation (DPWM) researches use multiple clock inputs and long D flip-flop (DFF) arrays, which makes scaling to different DPWM frequencies challenging. This brief demonstrates a DPWM that utilizes a single clock and a Matrix shift array, allowing it to be scaled to any frequency and reducing the effects of clock skew. It has a clock gating technique that selects a specific row of DFFs based on the required % duty cycle. The DPWM design has a dead time generator to prevent shoot-throughs. The DPWM has been fabricated using UMC 180-nm CMOS process. The performance and functionality of the DPWM have been verified through the measured comparisons of % duty ratio, dead time ($T_{dt}$), and output frequency ($f_{\text {out}}$) at input clock frequency ($f_{\text {clk}_{\text {in}}}$) equal to 10$\sim $100 MHz. The DPWM design has a maximum % duty ratio of 90.6%,$T_{dt}$= 1.8 ns, and$f_{\text {out}}$= 6.25 MHz with 3.4-mW power consumption at$f_{\text {clk}_{\text {in}}}$= 100 MHz.

For high-resolution, high-accuracy applications, re-cent DPWM (digital PWM) researches use long DFF arrays, resulting in clock skew that may compromise DPWM performance. This study proposed a DPWM based on a matrix phase shifter and clock gating technique which only selects a specific row of DFFs during operation depending on the required level of$\mathrm{V}_{o}$. The proposed design minimizes the clock skew caused by redundant DFF array clock activity. In addition, it uses a single clock and does not need any extra signal for synchronization. It has a dead-time generator that prevents shoot-through. The proposed DPWM has been implemented in UMC 180-nm CMOS technology where an overall chip and core area of 1285 x 1285$\mu \mathbf{m}^{2}$and 725.1 x 282.8$\mu \mathbf{m}^{2}$are used, respectively. The all-PVT corner post-layout simulation confirmed the functionality of the design with a maximum duty cycle of 90.6% at$\mathbf{C}_{load}=60\ \text{pF}$and$\mathbf{f}_{clk}=100$MHz.