Understanding complex physical systems often requires integrating data from multiple diagnostics, each with limited resolution or coverage. We present a machine learning framework that reconstructs synthetic high-temporal-resolution data for a target diagnostic using information from other diagnostics, without direct target measurements during the inference. This multimodal super-resolution technique improves diagnostic robustness and enables monitoring even in case of measurement failures or degradation. Applied to fusion plasmas, our method targets edge-localized modes (ELMs), which can damage plasma-facing materials. By reconstructing super-resolution Thomson Scattering data from complementary diagnostics, we uncover fine-scale plasma dynamics and validate the role of resonant magnetic perturbations (RMPs) in ELM suppression through magnetic island formation. The approach provides new observation supporting the plasma profile flattening due to these islands. Our results demonstrate the framework’s ability to generate high-fidelity synthetic diagnostics, offering a powerful tool for ELM control development in future reactors like ITER. The approach is broadly transferable to other domains facing sparse, incomplete, or degraded diagnostic data, opening new avenues for discovery.

Gate sizing is a critical step in achieving the target power, performance, and area (PPA) in chip design. In recent years, machine learning (ML) methods have recently emerged as a new paradigm for gate sizing. Their promising results have gained attention; however, the practical applicability and performance of existing works is limited by at least one of the following factors: (1) long runtime due to test-time optimization or autoregressive prediction; (2) limited exploration of architectural choices; (3) an overly simplified data representation, known as a homogeneous graph, which merges pins and cells into a single node. To improve both practicality and performance, we introduce a novel MLbased gate sizer, dubbed DPH-Sizer, which directly predicts the appropriate gate sizes using a heterogeneous graph that separates cells and their pins into distinct nodes. This heterogeneous graph explicitly captures the relationships between different circuit elements, leading to enhanced performance. Lastly, we propose InterCell and Intra-Cell GAT blocks to explicitly capture both intracell and inter-cell information. These are followed by transformer blocks, which are placed at the end of the GAT stack to capture global path-level features. In our experiments, we validate each of the proposed components and demonstrate that DPH-Sizer maintains power consumption within 2.0% on average while achieving improvements of 54.3% in timing (WNS) and 1.3% in area metrics.

As technology nodes advance and feature sizes shrink, the increasing complexity of design rules and routing congestion has resulted in greater design challenges and rising costs. Machine learning (ML) models offer significant potential to enhance design quality by enabling early prediction and optimization during the design flow. However, only a few works have validated the effectiveness of ML model when integrated to the traditional design flow. This paper will cover the effectiveness of ML-enhanced design workflow with some practical applications. Additionally, we will address which problems should be solved to achieve successful ML integration.

With significant advancements in various design methodologies, modern integrated circuits have experienced noteworthy improvements in power, performance, and area. Among various methodologies, design space optimization (DSO), which automatically explores electronic design automation (EDA) tool parameters for a given design, has been extensively studied in recent years. In this study, we propose an approach to fine-tuning an effective FPGA design space to suit a specific design. By utilizing our ML-based prediction and explainable artificial intelligence (XAI) approach, we quantify parameter contribution scores, which reveal the correlation between each parameter and the final timing results. Using the valuable insights from the parameter contribution scores, we can refine the design space only with effective parameters for subsequent timing optimization. During the optimization, our framework improved the maximum operating frequency by 26% on average in six test designs. To accomplish this, our framework required even 47% fewer FPGA compilations than the baseline, demonstrating its superior capacity for achieving fast convergence.

In recent years, post-place optimization has emerged as a critical stage in physical design, aiming to improve power, performance, and area (PPA). Among various optimization techniques, buffer insertion, gate sizing, and Vth assignment have become leading optimization techniques for decades. However, these techniques are traditionally applied sequentially, leading to a critical suboptimality problem. Each technique obtains its own iterations performed step by step, preventing the best-optimal optimization for a target instance. To address this limitation, we propose a novel reinforcement learning (RL) based post-place optimization framework that performs various optimization techniques simultaneously. Moreover, to overcome the persistent headache of chip design, timing and power trade-off, we employ multiple agents that target each specific objective. By leveraging deep RL and graph neural network (GNN), our framework models optimal policies, dynamically selecting the most effective action given a target instance. Consequently, our framework obtained an improved Pareto-frontier set compared to comparison baselines while exhibiting 80% and 43% improvements in total negative slack and leakage power, respectively. The results demonstrate that our method outperforms weighted-sum-based co-optimization methods in optimizing timing and power.

Tokamak is a torus-shaped nuclear fusion device that uses magnetic fields to confine fusion fuel in the form of plasma. Tearing instability in plasma is a major issue in which the magnetic field breaks and recombines in tokamak. This instability can lead to plasma disruption that terminates the fusion power generation and damages the plasma-facing wall materials. For a successful steady operation of a large-scale tokamak without disruption, it is required to predict and alarm the tearing instabilities well in advance to avoid them. In this work, we develop and validate a deep neural network-based multimodal prediction system that estimates the future tearing instability likelihood from multi-diagnostics signals in the DIII-D tokamak.