Brian Udugama

dblp:308/9046 · DBLP profile ↗
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3ranked-venue papers
2as first author
3since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Network security · 67% Hardware security and side channels · 33%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Network security
covert channel
0.912025
A Novel Covert Timing Channel for Cloud FPGAs · DAC 2025
Network security › covert channel
covert timing channel
0.912025
A Novel Covert Timing Channel for Cloud FPGAs · DAC 2025
Hardware security and side channels › hardware attacks
side-channel and fault attacks
0.912025
A Novel Covert Timing Channel for Cloud FPGAs · DAC 2025
Reconfigurable computing and FPGAs
cloud FPGA
0.312025
A Novel Covert Timing Channel for Cloud FPGAs · DAC 2025
YearPublicationVenuePosition
2025 A Novel Covert Timing Channel for Cloud FPGAs
abstract
This paper presents a novel covert timing channel (CTC) that enables a malicious entity to exfiltrate data from a benign cloud FPGA user without requiring dedicated outgoing messages from the cloud FPGA, minimizing the detection risk by both the victim and the cloud service provider. The proposed CTC exploits the handshake signals of the Advanced eXtensible Interface (AXI) protocol and interpacket delay of the Internet to establish the CTC from a cloud FieldProgrammable Gate Array (FPGA) to an off-cloud computer. This paper analyzes the bit-error rate (BER) of the AXI-based CTC under varying conditions and demonstrates its effectiveness in truly enabling remote power analysis attacks on cloud services, such as Amazon Web Services Elastic Compute Cloud (AWS EC2). The proposed CTC achieves a BER as low as 0.01988%.
Brian Udugama, Darshana Jayasinghe, Hassaan Saadat, Aleksandar Ignjatovic, Sri Parameswaran
DAC1
2024 Sensors for Remote Power Attacks: New Developments and Challenges
abstract
Power consumption as a side channel has garnered significant attention in security research. Traditional power attacks, also referred to as power analysis attacks, necessitated physical access to target devices to measure power consumption fluctuations for disclosing sensitive information. Recent developments, however, have revealed that field programmable gate arrays (FPGAs) in remote settings and cloud services are vulnerable to remote power analysis (RPA) attacks, avoiding the need for physical access. Understanding evolving threats and sensor methodologies is crucial for the development of robust defense strategies. Thus, this paper discusses two stealthy on-chip sensors, the Voltage-Induced Time Interval Sensor (VITI) and the Power to Pulse Width Modulation Sensor (PPWM), offering effective means for conducting RPA attacks.
Brian Udugama, Darshana Jayasinghe, Sri Parameswaran
ASPDAC1
2023 FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers
abstract
Field Programmable Gate Arrays (FPGAs) are increasingly ubiquitous. FPGAs enable hardware acceleration and reconfigurability. Any security breach or attack on critical computations occurring on an FPGA can lead to devastating consequences. Side-channel attacks have the ability to reveal secret information, such as secret keys from cryptographic circuits running on FPGAs. Power dissipation (PA), Electromagnetic (EM) radiation, fault injection (FI) and remote power dissipation (RPA) attacks are the most compelling and noninvasive side-channel attacks demonstrated on FPGAs. This paper discusses two PA attack countermeasures (QuadSeal and RFTC) and one RPA attack countermeasure (UCloD) in detail to protect FPGAs.
Darshana Jayasinghe, Brian Udugama, Sri Parameswaran
ASP-DAC2