Resolving the design rule checking (DRC) violations at the pre-route stage is critically important to reduce the time-consuming design closure process at the post-route stage. Recently, noticeable methodologies have been proposed to predict DRC hotspots using Machine Learning based prediction models. However, little attention has been paid to how the predicted DRC violations can be effectively resolved. In this paper, we propose a pre-route DRC violation resolution methodology that is tightly coupled with fully compatible prediction model. Precisely, we devise different resolution strategies for two types of DRC violations: (1) pin accessibility (PA)-related and (2) routing congestion (RC)-related. To this end, we develop a fully predictable ML-based model for both PA and RC-related DRC violations, and propose completely different resolution techniques to be applied depending on the DRC violation type informed by the compatible prediction model such that for (1) PA-related DRC violation, we extract the DRC violation mitigating regions, then improve placement by formulating the whitespace redistribution problem on the regions into an instance of Bayesian Optimization problem to produce an optimal cell perturbation, while for (2) RC-related DRC violation, we manipulate the routing resources within the regions that have high potential for the occurrence of RC-related DRC violation. Through experiments, it is shown that our methodology is able to resolve the number of DRC violations by 26.54%, 25.28%, and 20.34% further on average over that by a conventional flow with no resolution, a commercial ECO router, and a state-of-the-art academic predictor/resolver, respectively, while maintaining comparable design quality.

The three major tasks in standard cell layout synthesis are transistor folding, transistor placement, and in-cell routing, which are tightly interrelated, but generally performed one at a time to reduce the extremely high complexity of design space. In this article, we propose an integrated approach to the two problems of transistor folding and placement. Precisely, we propose an optimal algorithm of search tree-based design space exploration, devising a set of effective speeding up techniques as well as dynamic programming-based fast cost computation. Our algorithm also incorporates the minimum oxide diffusion (OD) jog constraint, which closely relies on both of transistor folding and placement. To our knowledge, this is the first work that tries to simultaneously solve the two problems. In addition, to make an effective cell layout synthesis flow down to in-cell routing, we provided a fast in-cell routability estimation metric to be used in transistor placement and a method to explore cell layouts by varying the cell size constraint. Through experiments with the transistor netlists and design rules in the ASAP 7-nm library, it is shown that our proposed method is able to synthesize fully routable cell layouts of minimal size within very fast time for each netlist, outperforming the cell layout quality in the ASAP 7-nm library, which otherwise, may take several hours or days to manually complete layouts of the quality level comparable to ours.

Advanced technology nodes face challenges related to DRVs (design rule violations), primarily due to (1) pin inaccessibility and routing on congested region. While various ML (machine learning) techniques have been introduced to address these issues during placement, aggregating data on pin accessibility and routing congestion for ML model training has proven very challenging. This study presents an innovative ML-based approach to DRC (design rule check) hotspot prediction that effectively captures the combined impact of pin accessibility and routing congestion. Specifically, we introduce the concept of pin proximity graph, which accurately represents spatial information regarding cell I/O pins and pin-to-pin disturbance relationships. We then propose a novel ML model called PGNN, which seamlessly integrates GNN (Graph Neural Network) and U-net. In this approach, GNN handles the incorporation of pin accessibility information derived from the pin proximity graph while U-net extracts routing congestion information from grid-based features. Additionally, we solidify the capability of our prediction model toward ensuring the practical applicability and sustainability of our model by integrating two learning methodologies into our model training framework. Those are (1) transfer learning whose objective is to retain the same level of prediction accuracy in spite of not having enough data on the new process node and (2) incremental learning whose objective is to reduce the train time while maintaining the model accuracy in similar quality when new circuits are added.

An accurate DRC (design rule check) hotspot prediction at the placement stage is essential in order to reduce a substantial amount of design time required for the iterations of placement and routing. It is known that for implementing chips with advanced technology nodes, (1) pin accessibility and (2) routing congestion are two major causes of DRVs (design rule violations). Though many ML (machine learning) techniques have been proposed to address this prediction problem, it was not easy to assemble the aggregate data on items 1 and 2 in a unified fashion for training ML models, resulting in a considerable accuracy loss in DRC hotspot prediction. This work overcomes this limitation by proposing a novel ML based DRC hotspot prediction technique, which is able to accurately capture the combined impact of items 1 and 2 on DRC hotspots. Precisely, we devise a graph, called pin proximity graph, that effectively models the spatial information on cell I/O pins and the information on pin-to-pin disturbance relation. Then, we propose a new ML model, called PGNN, which tightly combines GNN (graph neural network) and U-net in a way that GNN is used to embed pin accessibility information abstracted from our pin proximity graph while U-net is used to extract routing congestion information from grid-based features. Through experiments with a set of benchmark designs using Nangate 15nm library, our PGNN outperforms the existing ML models on all benchmark designs, achieving on average 7.8~12.5% improvements on F1-score while taking 5.5× fast inference time in comparison with that of the state-of-the-art techniques.

The three major tasks in standard cell layout synthesis are transistor folding, transistor placement, and in-cell routing, which are tightly inter-related, but generally performed one at a time to reduce the extremely high complexity of design space. In this paper, we propose an integrated approach to the two problems of transistor folding and placement. Precisely, we propose a globally optimal algorithm of search tree based design space exploration, devising a set of effective speeding up techniques as well as dynamic programming based fast cost computation. In addition, our algorithm incorporates the minimum OD (oxide diffusion) jog constraint, which closely relies on both of transistor folding and placement. To our knowledge, this is the first work that tries to simultaneously solve the two problems. Through experiments with the transistor netlists and design rules in the ASAP 7nm library, it is shown that our proposed method is able to synthesize fully routable cell layouts of minimal size within 1 second for each netlist, outperforming the cell layout quality in the ASAP 7nm library, which otherwise, may take several hours or days to manually complete layouts of the quality level comparable to ours.