Demo Data from EDBT 2026 / reviewers in the wild / expert
Yu-Neng Wang
dblp:309/4651
· DBLP profile ↗
2ranked-venue papers
2as first author
2since 2021 · last 2024
0000-0003-2967-4431ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 44% Electronic design automation · 44% Emerging computing paradigms · 13% | |
| Software engineering, system software, and programming languages
1 paper |
Programming languages and type systems · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Programming languages and type systems
domain-specific languages |
0.8 | 1 | 2024 | Design of Novel Analog Compute Paradigms with Ark · ASPLOS (2) 2024 |
Integrated circuit design › analog and mixed-signal circuits
analog circuit design |
0.8 | 1 | 2024 | Design of Novel Analog Compute Paradigms with Ark · ASPLOS (2) 2024 |
Electronic design automation
analog circuit design automation |
0.8 | 1 | 2024 | Design of Novel Analog Compute Paradigms with Ark · ASPLOS (2) 2024 |
Emerging computing paradigms
analog computing |
0.2 | 1 | 2024 | Design of Novel Analog Compute Paradigms with Ark · ASPLOS (2) 2024 |
Methods — techniques the papers use, named apart from their topics
formal verification · 1.5dynamical system compilation · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Design of Novel Analog Compute Paradigms with ArkabstractPrevious efforts on reconfigurable analog circuits mostly focused on specialized analog circuits, produced through careful co-design, or on highly reconfigurable, but relatively resource inefficient, accelerators that implement analog compute paradigms. This work deals with an intermediate point in the design space: specialized reconfigurable circuits for analog compute paradigms. This class of circuits requires new methodologies for performing co-design, as prior techniques are typically highly specialized to conventional circuit classes (e.g., filters, ADCs). In this context, we present Ark, a programming language for describing analog compute paradigms. Ark enables progressive incorporation of analog behaviors into computations, and deploys a validator and dynamical system compiler for verifying and simulating computations. We use Ark to codify the design space for three different exemplary circuit design problems, and demonstrate that Ark helps exploring design trade-offs and evaluating the impact of non-idealities to the computation. Yu-Neng Wang, Glenn E. R. Cowan, Ulrich Rührmair, Sara Achour |
ASPLOS (2) | 1 |
| 2021 | Compatible Equivalence Checking of X-Valued CircuitsabstractThe X-value arises in various contexts of system design. It often represents an unknown value or a don't-care value depending on the application. Verification of X-valued circuits is a crucial task but relatively unaddressed. The challenge of equivalence checking for X-valued circuits, named compatible equivalence checking, is posed in the 2020 ICCAD CAD Contest. In this paper, we present our winning method based on X-value preserving dual-rail encoding and incremental identification of compatible equivalence relation. Experimental results demonstrate the effectiveness of the proposed techniques and the outperformance of our approach in solving more cases than the commercial tool and the other teams among the top 3 of the contest. Yu-Neng Wang, Yun-Rong Luo, Po-Chun Chien, Ping-Lun Wang, Hao-Ren Wang, Wan-Hsuan Lin, Jie-Hong Roland Jiang, Chung-Yang Huang |
ICCAD | 1 |