Domain-specific HWACC-rich platforms blend high performance and efficiency presenting an opportunity to recover nonrecurring engineering costs through wider deployment for many applications. However, the design of such platforms is immensely challenging, partly due to the design space size. MG-DmDSE (Zhang et al., 2023) allocates domain platforms catering to multiple applications. To cope with complexity, it employs a genetic algorithm and heuristics. While this is a typical approach in design space exploration (DSE), it cannot guarantee optimality. Exact solutions could be obtained with integer linear programming (ILP). Yet, the multiapplication DSE presents aggregation challenges as applications might have widely different performance, leading to nonlinear aggregation techniques in previous work that ILPs cannot employ. This work introduces DmTSAR-ILP, an ILP-based platform allocation method that simultaneously considers all applications in a domain. DmTSAR-ILP captures the same underlying analytical model as MG-DmDSE and can explore its domain application set. To enable our linear domain-level formulation, we introduce the average performance achievement metric (APA), offering an ILP-friendly, fair aggregation across domain applications. To highlight benefits of DmTSAR-ILP, a domain platform for 40 OpenVX apps is generated (across varying area budgets). For all area budgets, DmTSAR-ILP platforms perform better or identical to MG-DmDSE even in their original metric. The proposed APA aggregation is fair, allowing more applications (55% vs 37.5% of applications in MG-DmDSE) to be fully accelerated on the generated platform. For the$0.1~\mathbf {mm}^{2}$area budget, DmTSAR-ILP’s platform increases application throughput by 22.5% over MG-DmDSE’s platform. DmTSAR-ILP is 70x faster on average than the heuristic-based MG-DmDSE by leveraging an ILP formulation that considers all applications simultaneously and recent advances in mixed-integer programming solver performance.

Domain-specific HWACC-rich platforms blend high performance & efficiency presenting an opportunity to recover non-recurring engineering costs through wider deployment for many applications. However, the design of such platforms is immensely challenging, partly due to the design space size.MG-DmDSE [1] allocates domain platforms catering to multiple applications. To cope with complexity, it employs a genetic algorithm and heuristics. While this is a typical approach in DSE, it cannot guarantee optimality. Exact solutions could be obtained with integer linear programming (ILP). Yet, the multi-application DSE presents aggregation challenges as applications might have widely different performance, leading to non-linear aggregation techniques in previous work that ILPs cannot employ.This work introduces DmTSAR-ILP, an ILP-based platform allocation method that simultaneously considers all applications in a domain. DmTSAR-ILP captures the same underlying analytical model as MG-DmDSE and can explore its domain application set. To enable our linear domain-level formulation, we introduce the average performance achievement metric (APA), offering an ILP-friendly, fair aggregation across domain applications.To highlight benefits of DmTSAR-ILP, a domain platform for 40 OpenVX apps is generated (across varying area budgets). For all area budgets, DmTSAR-ILP platforms perform better or identical to MG-DmDSE even in their original metric. The proposed APA aggregation is fair, allowing more applications (55% vs 37.5% of applications in MG-DmDSE) to be fully accelerated on the generated platform. For the 0.1 mm 2 area budget, DmTSAR-ILP’s platform increases application throughput by 22.5% over MG-DmDSE’s platform. DmTSAR-ILP is 70x faster on average than the heuristic-based MG-DmDSE by leveraging an ILP formulation that considers all applications simultaneously and recent advances in MIP solver performance.

Automatic design space exploration (DSE) is key in hardware-software (HW/SW) co-design. To cope with the large design space, explorations are often heuristic-based and/or approximate yielding potentially locally optimal solutions. Without knowing the globally optimal solution, strong assertions about performance upper/lower bounds cannot be made. In contrast, integer linear programming (ILP) formulations can produce exact (optimal) solutions. Previous ILP-based formulations, however, lack support for tile-based architectures and realistic synchronization models, limiting their DSE capabilities. This work introduces a tile-based, synchronization-aware ILP (TSAR-ILP) formulation that overcomes previous limitations. With TSAR-ILP, the allocation/binding problems are introduced and formalized, attaining optimal solutions for mapping streaming applications onto template platforms. Using TSAR-ILP, this work explores a hardware accelerator-rich (HWACC-rich) platform with direct HWACC-to-HWACC communication under HW area constraints for 40 OpenVX applications. To illustrate design opportunities given by: 1) the ILP formulation and 2) direct HWACC-to-HWACC communication, this article analyzes the impact of job size. Results show that selecting smaller job sizes yields performance improvements and less area usage at the cost of slightly increased synchronization overhead. A job size reduction from 1 kB to 256 bytes gives$3.51\times $average performance increase across 40 applications. Finally, DSE with TSAR-ILP is shown not to be prohibitive through scalability analysis using a set of 5000 synthetic applications with varying size (10–125 nodes), with 94.3% of applications successfully achieving optimal solutions under 60 s.