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Jinhao Li 0007

dblp:309/6695-7 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2026
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 56% Hardware accelerators and domain-specific architectures · 44%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.812024
APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Memory systems
processing-in-memory
0.812024
APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Memory systems › processing-in-memory
processing-in-MRAM
0.812024
APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network acceleration
quantized CNN accelerator
0.812024
APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Memory systems › non-volatile memory
magnetic random access memory
0.212024
APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Memory systems
non-volatile memory
0.212024
APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024

Methods — techniques the papers use, named apart from their topics

bit-level sparsity · 0.8bit-fusion format · 0.8
YearPublicationVenuePosition
2026 Design and Implementation of a Scalable 64 p-bits Ising Computing Chip with Integrated SOT-MTJs for Efficient Computing
Jinhao Li 0007, Jialiang Yin, Linying Liu, Chengyuan Sun, Hong-Xi Liu, Kaihua Cao, Zhaohao Wang, Wenlong Cai, He Zhang 0011
ISCAS2
2024 APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks
abstract
Quantized Convolutional Neural Network (QCNN) is an attractive approach that reduces hardware overheads, especially for energy-constrained systems. However, existing QCNNs still require non-trivial hardware resources and memory capacity in order not to compromise model accuracy. To address this issue, we propose an antiferromagnetic magnetic random-access memory (ARAM)-based processing-in-memory (PIM) system, leveraging bit-level sparsity. Three optimization techniques are proposed to optimize hardware resource utilization while preserving CNN accuracy. Firstly, the ARAM-based memory subsystem allows dynamic adaptation of variable bit-width across CNN layers. Secondly, the bit-level accelerator employs the bit-fusion format engineered for processing data from the ARAM subsystem. Thirdly, a customized data path within the RISC-V core guarantees efficient instruction processing to the ARAM-based memory subsystem and bit-level accelerator, enabling optimal bit-level data transmission and computation. Experimental results demonstrate that this design remarkably reduces data movement by 50%-83% across existing CNNs. Compared to state-of-the-art designs, it enhances throughput and latency by an average of 5x and 10x, respectively. In addition, this design achieves speedups between 1.63x and 2.96x, outstripping other designs in AlexNet, VGG16, and ResNet18 benchmarks.
Yueting Li 0001, Daoqian Zhu, Jinhao Li 0007, Ao Du, Yue Zhang 0010, Weisheng Zhao 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4