Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Nicholas Mosier

dblp:309/7020 · DBLP profile ↗
← Back
3ranked-venue papers
3as first author
3since 2021 · last 2026
0000-0003-3705-8161ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author · 2 since 2021Security and privacy · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
3 papers
Hardware security and side channels · 100%
Software engineering, system software, and programming languages
2 papers
Compilers and program optimization · 100%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 85% Memory systems · 15%

Topics — the 9 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › microarchitectural attacks › transient execution attack › speculative execution attack
spectre defense
1.822026
Protean: A Programmable Spectre Defense · HPCA 2026
Serberus: Protecting Cryptographic Code from Spectres at Compile-Time · SP 2024
Hardware security and side channels › microarchitectural attacks › transient execution attack
speculative execution attack
1.822026
Protean: A Programmable Spectre Defense · HPCA 2026
Serberus: Protecting Cryptographic Code from Spectres at Compile-Time · SP 2024
Compilers and program optimization
secure compilation
1.012026
Protean: A Programmable Spectre Defense · HPCA 2026
Processor architecture and microarchitecture › instruction set architecture
ISA extension
1.012026
Protean: A Programmable Spectre Defense · HPCA 2026
Hardware security and side channels
microarchitectural attacks
0.612022
Axiomatic hardware-software contracts for security · ISCA 2022
Hardware security and side channels › microarchitectural side channel
microarchitectural leakage
0.612022
Axiomatic hardware-software contracts for security · ISCA 2022
Hardware security and side channels › microarchitectural attacks
transient execution attack
0.612022
Axiomatic hardware-software contracts for security · ISCA 2022
Hardware security and side channels
side-channel countermeasures
0.312026
Protean: A Programmable Spectre Defense · HPCA 2026
Memory systems › memory consistency
memory consistency model
0.212022
Axiomatic hardware-software contracts for security · ISCA 2022

Methods — techniques the papers use, named apart from their topics

prottrack · 3.0protdelay · 3.0ProtISA · 3.0ProtCC · 3.0taint analysis · 1.5constant-time code analysis · 1.5static analysis · 1.1axiomatic modeling · 1.1
YearPublicationVenuePosition
2026 Protean: A Programmable Spectre Defense
abstract
We present the PROTEAN Spectre defense—the first to be altogether comprehensive, covering all side-channels and speculation; programmer-transparent, requiring no source modifications; and programmable, tailoring its hardware protections to software's security needs. Several Spectre defenses offer the first two features, but protect a hardware-defined subset of architectural state from transiently leaking. Meanwhile, many Spectrevulnerable programs process secrets in ways that such rigid protections cannot both performantly and fully secure. Protean overcomes this limitation through: (1) ProtISA, an ISA extension that allows software to tell hardware which architectural registers and memory bytes require protection from transiently leaking at each program point; (2) ProtCC, a compiler that automatically infers and programs ProtISA protections for vulnerable code with minimal user input; and (3) ProtDelay and ProtTrack, two alternative hardware mechanisms that performantly enforce software-defined ProtISA protections. By flexibly tailoring a hardware Spectre defense to a program's data protection needs, Protean significantly reduces the overhead of fully securing vulnerable programs. With ProtDelay/ProtTrack, it averages$0.27 \mathrm{x} / 0.18 \mathrm{x}$and$0.42 \mathrm{x} / 0.34 \mathrm{x}$of the runtime overhead of the best secure baseline for programs with and without mixed security needs, respectively, at lower/comparable hardware complexity.
Nicholas Mosier, Hamed Nemati, John C. Mitchell, Caroline Trippel
HPCA1
2024 Serberus: Protecting Cryptographic Code from Spectres at Compile-Time
abstract
We present Serberus, the first comprehensive mitigation for hardening constant-time (CT) code against Spectre attacks (involving the PHT, BTB, RSB, STL, and/or PSF speculation primitives) on existing hardware. Serberus is based on three insights. First, some hardware control-flow integrity (CFI) protections restrict transient control-flow to the extent that it may be comprehensively considered by software analyses. Second, conformance to the accepted CT code discipline permits two code patterns that are unsafe in the post-Spectre era. Third, once these code patterns are addressed, all Spectre leakage of secrets in CT programs can be attributed to one of four classes of taint primitives—instructions that can transiently assign a secret value to a publicly-typed register. We evaluate Serberus on cryptographic primitives in the OpenSSL, Libsodium, and Hacl* libraries. Serberus introduces 21.3% runtime overhead on average, compared to 24.9% for the next closest state-of-the-art software mitigation, which is less secure.
Nicholas Mosier, Hamed Nemati, John C. Mitchell, Caroline Trippel
SP1
2022 Axiomatic hardware-software contracts for security
abstract
We propose leakage containment models (LCMs)---novel axiomatic security contracts which support formally reasoning about the security guarantees of programs when they run on particular microarchitectures. Our core contribution is an axiomatic vocabulary for formalizing LCMs, derived from the established axiomatic vocabulary for formalizing processor memory consistency models. Using this vocabulary, we formalize microarchitectural leakage---focusing on leakage through hardware memory systems---so that it can be automatically detected in programs and provide a taxonomy for classifying said leakage by severity. To illustrate the efficacy of LCMs, we first demonstrate that our leakage definition faithfully captures a sampling of (transient and non-transient) microarchitectural attacks from the literature. Second, we develop a static analysis tool based on LCMs which automatically identifies Spectre vulnerabilities in programs and scales to analyze real-world crypto-libraries.
Nicholas Mosier, Hanna Lachnitt, Hamed Nemati, Caroline Trippel
ISCA1