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James D. Plummer

dblp:31/10712 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
semiconductor technology
0.412020
A Density Metric for Semiconductor Technology [Point of View] · Proc. IEEE 2020
Integrated circuit design › semiconductor devices › device scaling
MOSFET scaling
0.012001
Material and process limits in silicon VLSI technology · Proc. IEEE 2001
Integrated circuit design › semiconductor technology › semiconductor process technology
silicon technology
0.012001
Material and process limits in silicon VLSI technology · Proc. IEEE 2001
Integrated circuit design › semiconductor technology
semiconductor process technology
0.012001
Material and process limits in silicon VLSI technology · Proc. IEEE 2001
YearPublicationVenuePosition
2020 A Density Metric for Semiconductor Technology [Point of View]
abstract
Since its inception, the semiconductor industry has used a physical dimension (the minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. As a replacement, we propose a density metric, which aims to capture how advances in semiconductor device technologies enable system-level benefits. The proposed metric can be used to gauge advances in future generations of semi-conductor technologies in a holistic way, by accounting for the progress in logic, memory, and packaging/integration technologies simultaneously.
H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin
Proc. IEEE8
2020 Scanning the Issue
abstract
This month’s issue offers insight into efficient compression and execution of DNNs, the challenge of connecting rural areas, and the clique problem in wireless communication. which
H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin, Lei Deng 0003, Song Han 0003, Luping Shi, Yuan Xie 0001, Elias Yaacoub, Mohamed-Slim Alouini, Ahmed Douik, Hayssam Dahrouj, Tareq Y. Al-Naffouri
Proc. IEEE8
2001 Material and process limits in silicon VLSI technology
abstract
The integrated circuit (IC) industry has followed a steady path of shrinking device geometries for more than 30 years. It is widely believed that this process will continue for at least another ten years. However there are increasingly difficult materials and technology problems to be solved over the next decade if this is to actually occur, and beyond ten years there is great uncertainty about the ability to continue scaling metal-oxide-semiconductor field-effect transistor (MOSFET) structures. This paper describes some of the the most challenging materials and process issues to be faced in the future and where possible solutions are known, describes these potential solutions. The paper is written with the underlying assumption that the basic metal-oxide-semiconductor (MOS) transistor will remain the dominant switching device used in ICs and it further assumes that silicon will remain the dominant substrate material.
James D. Plummer, Peter B. Griffin
Proc. IEEE1