In this paper, we proposed an improved method in the prediction of stage-specific TREs associated with four classes of developmentally regulated genes in Dictyostelium discoideum. TRE selection with a direct comparison of e-scores produced lots of the false positive results. In order to reduce false-positive prediction, we applied a normalization method to e-scores and predicted TREs in each developmentally regulated Dd gene sequence. Among the top 25 putative TREs in vegetative and culmination stage, we found two experimentally known TREs out of 6 known TREs in the TRANSFAC database. We also predicted five TREs experimentally known from the literature in the simulation results.

Jung-Hwan Kim School of Computer Science and Engineering Seoul National University Shilim-dong, Kwanak-gu, Seoul, 151-742 Korea [email protected] Sung-Soon Choi School of Computer Science and Engineering Seoul National University Shilim-dong, Kwanak-gu, Seoul, 151-742 Korea [email protected] Byung-Ro Moon School of Computer Science and Engineering Seoul National University Shilim-dong, Kwanak-gu, Seoul, 151-742 Korea [email protected]

Finding transcription regulatory elements (TREs) is one of most important tasks in current bioinformatics and functional genomics and is the first step to discover regulatory mechanisms of gene expression. The goal of this paper is to detect class-specific TREs associated with four classes of developmentally regulated genes in Dictyostelium discoideum (Dd) with statistically significant measure. Applying a DP matching to 5' UTR sequences of Dd with generated candidate TREs, we calculate the evaluation score (E-score) for given candidate TREs. Based on the proposed selection criteria of TREs, we choose putative class-specific TREs among candidate TREs in each developmentally regulated class of Dd. According to the simulation result with 49 sequences in V expression stage, 43 in A, 42 in S, and 47 in C, we predicted class-specific putative TREs, corresponding to a P /spl les/ 10/sup -3/ such as "aataattt", "attacaaa", and "attaatat" in V, "ttattcta", "atgtgtta", and "aaaattga" in A, "atttcaat", "aataattg", and "acaacaac" in S, "aaaaaatt", "ttaataat", and "atagtttt" in C expression stage of Dd. We could achieve 17.8 times faster TRE detection via parallel computing algorithm with 32 processor machines.

Ensuring the signal integrity even under pico-second switching-time in PCBs (printed circuit boards) as well as in VLSI chips is one of the most important goals in a PCB design. To achieve the goal, we propose a novel methodology of the PCB trace design in which the traces are regarded as segmental-transmission-lines of individual impedances. Also, the impedances are optimized by minimizing signal distortions due to multiple reflections in the transmission lines through genetic algorithms. Our design system shows excellent experimental results which achieves almost ideal signal wave forms without any signal distortion.

We present the performance gain of dual smart antennas with adaptive combining at handsets for the 3GPP W-CDMA system. The adaptive algorithm based on the normalized least-mean-square (N-LMS) algorithm is employed, in which antenna weights are recursively obtained. To obtain the channel profile, we adopted the GBSB (geometrically based single bounce) elliptical and circular models. The simulation results show that the dual smart antenna system with adaptive combining performs better than a single antenna system and its performance gain is 3.3 dB for the GBSB elliptical model at BER of 5/spl times/10/sup -2/ and 5.5 dB for the GBSB circular model. The higher performance gain is achieved as the mobile velocity decreases.

In this paper, we present a new genetic-algorithm-based design methodology for reasoning VLSI chips, called as LoDETT (logic design with the evolved truth table). In LoDETT, each task's case database is transformed into truth tables, which are evolved to obtain generalization capability (i.e. rules behind the past cases) through genetic algorithms. Digital circuits are synthesized from the evolved truth-tables. Parallelism in each task can be embedded directly in the circuits by the direct hardware implementation of the case database. We applied LoDETT to the English pronunciation reasoning (EPR) problem, resulting in a GATalk chip. A GATalk chip has been designed with about 270K gates, and its reasoning time is about 100 ns for each phoneme. A prototype of the GATalk chip has been implemented using Xilinx XC4010 FPGA chips. It achieved a reasoning accuracy of 81.9% which is almost the same accuracy as NETTalk in neural networks and MBRTalk in parallel AI.

We propose a parallel SOM algorithm to speedup the fundamental SOM calculation using parallel computer environments. In the parallel SOM algorithm synaptic weights are updated in parallel corresponding to multiple stimuli (inputs). Parallelism in the proposed algorithm is based on the analogy of the biological neural networks in which neurons respond to the stimuli in parallel. Performance is evaluated by implementing the newly developed performance simulator in a personal computer-cluster under the message passing interface library (MPI) environment. A speedup ratio of about 5.0 is achieved with 8 processors (personal computers) when the width of the neighborhood function is less than 5% of the total number of neurons in the SOM network.

The self-organizing map (SOM) implemented by wafer-scale integration (WSI) will provide significantly high speed and desktop-size hardware for many practical applications such as pattern classification, image-processing, and robotics. Due to the synergistic effect of all neurons for ordering, the SOM-WSI is expected to reach the desired global-ordering state even in the presence of defective neurons. This fault tolerant capability, however, has not yet been studied. In this paper, we propose a fundamental SOM-WSI structure and its defect model. From the defect model, we derive a critical-stuck-output and show that if the defective neuron's stuck-output is larger than the critical-stuck-output, the defective SOM can eventually organize itself completely tolerating defects. In an ordinary digital design of a neuron, the critical-stuck-output is proved to be small. Therefore, we can expect high-fault tolerance in the SOM-WSI. Experiments are carried out by injecting defective neurons in a neurocomputer currently used as a prototype of the SOM-WSI. The experimental result agrees well with the proposed theory. In addition, we derive an equation to estimate the degree of fault-tolerance in the SOM hardware by expanding the critical-stuck-output calculation. The derived equation can be used to determine the fundamental design parameters in the SOM-WSI as well as other neurocomputer designs.

The authors propose to set up assignment rules based on the available interconnection resources of 2-D processor arrays. The reconfiguration of 2-D processor arrays is guided by the assignment rules, such that logical cells are always connected through the available interconnection resources. The advantage of the proposed approach is the easy adaptation to various system requirements, by adjusting assignment rules. The proposed reconfiguration algorithm can be extended to arrays with clustered faulty cells, overcoming the weakness of fixed domain approaches.>

A novel reconfiguration scheme is proposed to achieve a highly successful reconfiguration rate for two-dimensional processor arrays with fixed interconnection resources. The authors use a flexible spare allocation scheme and thereby achieve a spare allocation pattern which maximizes the utilization of the given interconnection resources. However, some spare allocations may not result in the successful reconfiguration of a logic array due to the lack of necessary resources. The rationale behind this approach is that the probability of the occurrence of allocation patterns causing such resource conflicts is pretty low. Furthermore, the rare resource conflicts may be resolved by the proposed resolution techniques. By utilizing the given interconnection resources much more efficiently, the proposed scheme achieves a higher reconfiguration rate than a previous design of similar approach. The complexity of the reconfiguration algorithm is O(N/sup 2/).>

The authors propose a unified approach to the design of the fault-tolerant systolic arrays incorporating design for testability, a testing scheme, a reconfiguration algorithm, time-complexity analysis of the proposed reconfiguration algorithm, and yield analysis. A main feature of the proposed designs is that multiple processing elements in a 2-D array can be tested simultaneously, thus reducing the testing time significantly. Another feature is that with the introduction of delay registers, the proposed reconfiguration algorithm reconfigures a faulty 2-D systolic array into a fault-free array without reducing throughput. The overall aim is to provide a design for a 2-D systolic array that produces high yield in VLSI/WSI implementations.>