We describe the Ignite Distributed Collaborative Scientific Visualization System (IDCVS), a system which permits real-time interaction and visual collaboration around large data sets, with an initial emphasis on scientific data. The IDCVS offers such a collaborative environment, with real-time interaction on any device between users separated across the wide area. It provides seamless interaction and immediate updates even under heavy load and when users are widely separated: the design goal was to fetch a data set consisting of 30,000 points from a server and render it within 150ms, for a user anywhere in the world, and reflect changes made by a user in one location to all other users within a bound provided by network latency. The system was demonstrated successfully on a significant worldwide air pollution data set, with values on 10, 25, 50, and 100km worldwide grids, monthly over an 18-year period. It was demonstrated on a wide variety of clients, including laptop, tablet, and smartphone.

We present an application of the Java TM programming language to specify and implement reactive real-time systems. We have developed and tested a collection of classes and methods to describe concurrent modules and their asynchronous communication by means of signals. The control structures are closely patterned after those of the synchronous language Esterel , succinctly describing concurrency, sequencing and preemption. We show the user-friendliness and efficiency of the proposed technique by using an example from the automotive domain.

A trace driven methodology for logic synthesis and optimization is proposed. Given a logic description of a digital circuit C and an expected trace of input vectors T, an implementation of C that optimizes a cost function under application of T is derived. This approach is effective in capturing and utilizing the correlations that exist between input signals on an application specific design. The idea is novel since it proposes synthesis and optimization at the logic level where the goal is to optimize the average case rather than the worst case for a chosen cost metric. The paper focuses on the development of algorithms for trace driven optimization to minimize the switching power in multi level networks. The average net power reduction (internal plus I/O power) obtained on a set of benchmark FSMs is 14%, while the average reduction in internal power is 25%. We also demonstrate that the I/O transition activity provides an upper bound on the power reduction that can be achieved by combinational logic synthesis.

ion, which eliminates details that are of no importance when checking whether a design satisfies a particular property. ffl Decomposition, which consists of breaking the design at a given level of the hierarchy into components that can be designed and verified almost independently. These mechanisms can be applied to different classes of designs: from embedded controllers to computers, from microprocessors to digital-to-analog converters. They are not only useful in the verification process but also in the design process per se making verification itself unnecessary in some cases. For example, formalization of the design specifications is required for formal verification but it also helps in design transfer between different organizations eliminating the risk of losing knowledge about the design and its specifications, thus making verification before and after the transfer unnecessary. We argue that almost all advances in verification stem from the application of these three basic con...

Article Timed shared circuits: a power-efficient design style and synthesis tool Share on Authors: Luciano Lavagno Cadence Berkeley Laboratories, 1919 Addison Street, Suite 301, Berkeley-CA Cadence Berkeley Laboratories, 1919 Addison Street, Suite 301, Berkeley-CAView Profile , Patrick C. McGeer Cadence Berkeley Laboratories, 1919 Addison Street, Suite 301, Berkeley-CA Cadence Berkeley Laboratories, 1919 Addison Street, Suite 301, Berkeley-CAView Profile , Alexander Saldanha Cadence Berkeley Laboratories, 1919 Addison Street, Suite 301, Berkeley-CA Cadence Berkeley Laboratories, 1919 Addison Street, Suite 301, Berkeley-CAView Profile , Alberto L. Sangiovanni-Vincentelli Cadence Berkeley Laboratories, 1919 Addison Street, Suite 301, Berkeley-CA Cadence Berkeley Laboratories, 1919 Addison Street, Suite 301, Berkeley-CAView Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 254–260https://doi.org/10.1145/217474.217538Online:01 January 1995Publication History 21citation231DownloadsMetricsTotal Citations21Total Downloads231Last 12 Months1Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

An approach for fast discrete function evaluation based on multi-valued decision diagrams (MDD) is proposed. The MDD for a logic function is translated into a table on, which function evaluation is performed by a sequence of address lookups. The value of a function for a given input assignment is obtained with at most one lookup per input. The main application is to cycle-based logic simulation of digital circuits, where the principal difference from other logic simulators is that only values of the output and latch ports are computed. Theoretically, decision-diagram based function evaluation offers orders-of-magnitude potential speedup over traditional logic simulation methods. In practice, memory bandwidth becomes the dominant consideration on large designs. We describe techniques to optimize usage of the memory hierarchy.

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A common approach to performance optimization of circuits focuses on re-synthesis to reduce the length of all paths greater than the desired delay .We describe a new delay optimization procedure that optimizes only sensitizable paths greater than .Unlike previous methods that use topological analysis only, this method accounts for both functional and topological interactions in the circuit.Comprehensive experimental results comparing the proposed technique to a state-of-the-art performance optimization procedure are presented for combinational and sequential logic circuits.

We show very efficient methods to compute Walsh spectrum for logic functions with large numbers of inputs (30 or more) using Binary Decision Diagrams. The BUD structure is extended to have any integer values as leaf (constant) nodes. The result is an efficient representation for integer vectors and integer matrices. The proposed procedure works directly on an extended BDD for the logic function, and computes the full Walsh spectrum in the form of an extended BDD. The algorithm presented is a more efficient version of the matrix-multiplication method. Our method embeds the Walsh transform matrix implicitly into program code with recursive calls, which results in a significant speed improvement. Our algorithm has the same complexity as the fastest known Walsh algorithm, and utilizes a much more efficient data structure than traditional truth tables. Furthermore, in cases where the complete set of spectra coefficient is either infeasible or impractical, we also present a method to compute subsets of Walsh coefficients. We present experimental results showing that logic functions having more than 60 inputs which cannot be processed by other published methods can be computed within 30 seconds on Sparc 2.>

Article On computing the transitive closure of a state transition relation Share on Authors: Yusuke Matsunaga View Profile , Patrick C. McGeer View Profile , Robert K. Brayton View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 260–265https://doi.org/10.1145/157485.164884Online:01 July 1993Publication History 26citation439DownloadsMetricsTotal Citations26Total Downloads439Last 12 Months28Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Article Free Access Share on Espresso-signature: a new exact minimizer for logic functions Authors: Patrick McGeer View Profile , Jagesh Sanghavi View Profile , Robert Brayton View Profile , Alberto Sangiovanni Vincentelli View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 618–624https://doi.org/10.1145/157485.165069Online:01 July 1993Publication History 51citation464DownloadsMetricsTotal Citations51Total Downloads464Last 12 Months23Last 6 weeks5 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

We present a new algortthrn for exact two-ievei logzc opttmwatton which radtcally tmproves the Qutne -McCluskey (QM) procedure.The new aigorithm derzves the coverzng problem directly and amplicttly without generat~ng the set of all prtme zmplzcants.It then generates only those prime tmpltcants tnvolved in the covertng problem.We represent a set of primes by the

A technology-independent delay model is introduced. This model assumes that the technology mapper will attempt modest local restructuring of the network. It models the restructuring by producing a staggered network for each gate based on the arrival times of the fan-in signals. The delay of the network is calculated using the staggered network, and when compared to the delay reported by technology mapping, is found to be accurate and efficiently obtained.>

The authors introduce a novel method for the acceleration of general logic circuits based on the assumption that the delay of a circuit is its longest sensitizable (non-false) path. Hence, circuits are accelerated not by reducing path length but by making paths false. The method is based on generalizing the transformation used to obtain the bypass adder to automatically, in an area efficient way, reduce the delay of any combinational logic circuit with paths of varying length. The authors prove that a circuit realizing any function can be accelerated in this manner, give a general algorithm, and prove bounds on the size of the gain expected.>

The authors introduce an efficient method for generating the functional forms of path analysis problems. They demonstrate that the resulting function is linear in the size of the circuit. The functions are then tested for satisfiability either using a Boolean network satisfiability algorithm suggested by T. Larrabee (1989) or through the construction of BDDs. The effectiveness of the proposed approach is shown for timing analysis and robust path delay-fault test generation. This method also holds promise for both static and dynamic hazard analysis, and for test generation using all other delay-fault models, tau -irredundant fault models, and stuck-open fault models.>

The properties of delay-fault testability on dynamic CMOS logic circuits are investigated. It is demonstrated that the concepts of static sensitizability and robust path delay-fault (RPDF) testability are synonymous on these circuits, and that hence RPDF testability is somewhat easier on these circuits than on static logic circuits. It is also argued that a less restrictive testability condition than the RPDF criterion detects all path delay-faults which will affect the operation of the circuit. It is shown that the set of test vectors which satisfies this less-restrictive condition is exactly the union of the on-sets of the primary circuit outputs.>

We consider the false path problem on precharge/unate networks, more commonly known as dynamic CMOS networks. We demonstrate that the tight criterion of dynamic sensitization is robust on such networks, though it has been shown to be non-robust on general networks. Tighter bounds may be obtained on the length of the critical path in precharge/unate networks than in general static networks. We derive a dynamic programming procedure to find the longest dynamically sensitizable path in a precharge/unate network.

The problem of computing the observability don't-care set (nonobservability) for a node in a Boolean network is considered. This problem is generally intractable. Recurrence relations are given for two easily computed subsets of the fanout don't-care set. It is demonstrated that these are, in fact, subsets, and that other subsets appearing in the literature are subsets of those given by the authors.>

The set of multivariate Boolean functions over the variables χ1 …, χm is considered as the set of multilinear polynomials with coefficients in [0,1] over the literals {χ1, χ1, …, χm, χm}. We denote this set of polynomials as B[@@@@], and call the set of polynomial operations over them algebraic operations. It is shown that these polynomials, called logic expressions, have a unique algebraic prime factorization. An Ο(n log2 n) algorithm to find this factorization is presented. An improvement to the algorithm is presented which may reduce its average-case complexity to Ο(n).

We consider the elimination of false paths in combinational circuits. We give the single generic algorithm that is used to solve this problem, and demonstrate that it is parameterized by a Boolean function called the sensitization condition. We give two criteria which we argue that a valid sensitization condition must meet, and introduce four conditions that have appeared in the recent literature, of which two meet the criteria and two do not. We then introduce a dynamic programming procedure for the tightest of these conditions, the viability condition, and discuss the integration of all four sensitization conditions in the LLLAMA timing environment. We give results on the IWLS and ISCAS benchmark examples and on carry-bypass adders.

An m-function network on n primary inputs as forming an n+m-dimensional space is depicted. In this space there are points that can never occur due to mutual dependencies among the functions. This set has been called the satisfiability don't-care (SDC) set of the network and can be viewed as a function over the extended space. The authors demonstrate a sharp criterion for determining which transformations of the network preserve the SDC, and show that most of the operations of the MIS-II synthesis system preserve the SDC. This has importance for implications which are used in a number of network manipulations. This analysis also clarifies how other operations change the SDC, but in very predictable ways. It is shown that a most of the algebraic and some Boolean operations commonly used in logic synthesis preserve the testability of all but a single node in a network. An interesting example is algebraic division (or resubstitution) of one node into another.>