Six degrees of freedom (6DoF) pose estimation is a critical technique for applications involving humanoid robotics, autonomous driving, and virtual and augmented reality (VR/AR). Pose refinement plays a pivotal role in the 6DoF pose estimation, significantly enhancing accuracy by iteratively refining the initial pose derived from a single-shot pose estimation (SSPE) process. However, this iterative approach is time-and energy-consuming which is not suitable for resource-and power-constrained edge-devices. In this paper, we propose PRADO, an energy-efficient 6DoF pose refinement accelerator for edge applications. Several domain-specific explorations aimed at reducing processing latency and energy-consumption while maintaining high accuracy have been proposed, including an adaptive sparse correspondences sampling (ASCS) architecture to reduce redundant correspondences process, a hybrid static & dynamic pruning (HSDP) technique with co-designed hardware architecture to reduce computational complexity, and a cosine similarity-based adaptive early exit (CSAE2) technique to eliminate unnecessary iterations. Implemented and evaluated on the ZCU102 FPGA board, PRADO achieves the lowest processing latency of 61.2ms and energy consumption of 198.6mJ, and highest accuracy of 0.7112, outperforming state-of-the-art designs. Implemented with 28nm CMOS technology, PRADO achieves an even lower processing latency of 18.1ms and energy consumption of 12.6mJ.

In this paper, we present PM-Blade, an LSM-tree structured storage augmented with persistent memory (or non-volatile memory). PM-Blade utilizes persistent memory to optimize read performance and reduce write amplification, which are essential to Meituan’s online retail applications. Distinguished from existing designs, PM-Blade leverages persistent memory to drastically increase the capacity of the level-0 layer of LSM-tree. An enlarged level-0 layer allows a large amount of hot or warm data to be retained in persistent memory, enabling high read performance. At the same time, it works as a large write buffer that absorbs write amplification. To make the best of the design, we devised an internal compaction method and used a cost-based compaction strategy to maximize the utility of the level-0 layer. We implemented the compaction method using coroutines to improve its efficiency and resource utilization. We evaluated PM-Blade through extensive experiments, in which PM-Blade outperformed several open-source alternatives on standard benchmarks and a real-world workload of Meituan.

Fast and energy-efficient 6D pose estimation is essential for robotic applications, especially for picking robots in industrial scene. Introducing iterative pose refinement in the final stage of pose estimation pipeline can effectively improve the precision. However, this procedure can be very time consuming due to iterative convolutional neural network (CNN) inference on resource and power constrained platforms. In this paper, we propose a FPGA-based iterative pose refinement processing unit that achieves fast and energy-efficient pose estimation for picking robots. The design and implementation are based on a Xilinx Zynq UltraScale+ MPSoC. Our experimental results demonstrate that the proposed FPGA-Based processing unit is 21.78 times faster and 23.89 times more energy-efficient compared with the baseline, significantly enhances the speed and energy efficiency of pose refinement. The evaluation result on the datasets shows little accuracy drop compared to the baseline implementation.

Data acquisition time and accurate instrumentation are the most significant contributors to ADC test cost. For most ADC products, static linearity (INL/DNL) test is required. This paper presents a methodology for estimating an ADC's dynamic performance from its tested INL data, without requiring additional data acquisition or additional accurate sinusoidal sources. The tested INL(k) data is used to compute the power at harmonic frequencies and estimate ADC's dynamic specifications such as THD and SFDR. Memory and computation requirement is very small comparing to that in traditional spectral testing. When combined with a BIST approach for INL testing, this method offers a very low cost BIST solution to ADC dynamic performance testing. Both simulation and experimental results show that the proposed method can estimate THD and SFDR values accurately.

Linearity test and spectral test are two main contributors of ADC test cost which includes data acquisition time and accurate instrumentation. This paper presents a new method for estimating an ADC's spectral performance from its tested INL data. The method does not require additional dedicated test circuitry or data acquisition. The results from INL test are used to compute harmonic distortions and other spectral specifications of the ADC. Memory and computation requirements are very small comparing to those in traditional spectral testing. When combined with a BIST approach for INL testing, the proposed method offers a very low cost BIST solution to ADC spectral testing. Both simulation and experimental results show that the proposed method can estimate THD and SFDR values accurately.

In this paper, a low-cost test methodology for dynamic specifications of high precision sigma-delta (ΔΣ) analog-to-digital converters (ADCs) is presented. Dynamic testing of ADCs requires an input test stimulus with total harmonic distortion (THD) and signal-to-noise ratio (SNR) about 10dB better than the ADC under test. ΔΣ ADCs are inherently high resolution converters with excellent THD and SNR due to their inherent over-sampling, averaging and noise shaping properties. In the proposed test methodology, the back end digital and decimation filters of such converters are turned off and the digital pulse sequence at the output of the sigma-delta modulator is made externally observable for test purposes. It is seen that ENOB, THD and SNR of the converter can be determined with significantly increased sensitivity to device nonlinearities and noise allowing the use of less than ideal input stimulus than otherwise or significantly reduced test time. The back-end filters are then tested using traditional digital test techniques. Simulation results show the usefulness of the proposed test methodology.

Linearity testing of high resolution analog-to-digital Converters (ADCs) requires test instrumentation that has high precision digital-to-analog conversion (DAC) capability. Further, a large number of samples need to be collected for linearity testing of high resolution ADCs (18-24 bit) to guarantee test quality. In this paper a novel fast linearity testing approach is proposed for testing high resolution ADCs using a low precision DAC and a potentiometer. A polynomial fit of the transfer function of the ADC is generated using measurements made at intermediate code points. The test setup and analysis procedure makes no assumption about the linearity of the lower precision DAC or the potentiometer used to generate the ADC test stimulus. A least squares based polynomial fitting approach is used to characterize the transfer function of the ADC. The computed transfer function is then used to estimate the Integral Non-Linearity (INL) and the Differential Non-Linearity(DNL) of the system accurately. Software simulations and hardware experiments are performed to validate the proposed methodology.

This work presents a system identification-based reduced-code testing method for pipeline ADC’s linearity test. In the method, the pipeline ADC under test is identified by characterizing the two most critical parameters in each stage, the stage gain and the comparator offset. The transfer function is investigated to obtain the effects of the gain error and comparator offset on ADC’s linearity performance. With the measurements of a small set of specific transition levels or code bin widths, the system parameters of interest can be achieved using only straightforward linear calculations. The identified model is then used to compute the ADC’s full-code linearity performance. Comparing to standard histogram-based full-code linearity test methods, the proposed method can reduce the data capture time by a factor of several hundreds without appreciably degrading the testing accuracy. Both simulation results and experimental results are included to demonstrate the efficacy of the proposed method.

This work develops appropriate system and noise models, and a corresponding form of the Kalman filter to improve linearity test accuracy for high-resolution ADCs, while all necessary parameters are obtained from experimental measurements. The proposed algorithm can achieve comparable accuracy as that of the conventional histogram algorithm, by using a much smaller number of samples. This method can significantly shorten the test time and lower the cost of ADC production.

High-precision ADC testing is a challenging problem because of its stringent requirement on test signal's linearity. This work introduces a method using a nonlinear stimulus signal for testing linearity of high-resolution cyclic and pipelined ADCs by exploiting their architecture information. Simulation and experiments show that 16-bit ADCs can be tested to 1-LSB accuracy by using a 7-bit linear signal. This approach provides a solution to both the production and on-chip testing problems of high-resolution ADCs.

This work introduces a multi-segment bandgap reference circuit with self-calibration. Thermal characteristics of the bandgap circuit were modeled using test results under normal temperatures. With the characterization information, appropriate circuit parameters were calculated for different temperature intervals and used to adjust the inflection point of the bandgap curve as the temperature changes, in order for the reference circuit to achieve high thermal stability. Simulation results show that the proposed circuit can achieve a better than 0.5 ppm//spl deg/C temperature coefficient over a range of 140/spl deg/C. This circuit is compatible with most of the existing bandgap circuit structures and can be used in low-voltage designs.

In this paper, the well-known equation, which explicitly shows the temperature behavior of the I/sub C/-V/sub BE/ characteristics of the transistor, is applied to analyze a specific bandgap reference circuit. The theoretical analysis clearly characterizes some important features of the circuit, such as the value of the bandgap output, the relationship of the inflection point and the circuit parameters, the curvature of the bandgap curve and so on. Spectre simulations show a good consistency of the analysis. Based on the analysis, a new approach for designing high-precision references is also proposed.

This work introduces an efficient code-density linearity testing algorithm for ADCs that can achieve high accuracy within short test time. The proposed algorithm uses Kalman filtering to suppress the effect of errors in the histogram counts based on characteristics of input noise and circuit mismatches. Appropriate versions of the algorithm for ADCs of flash and pipelined architectures are introduced respectively. Simulation results show that this approach can reduce the INLkestimation error by over 50% and achieve desired accuracy with a much smaller number of samples as compared to the conventional algorithm. Simulation and experimental results show that the proposed algorithm can significantly shorten the linearity test time by a factor of 10 or higher. Therefore, it can enable test and help maintain the quality of high-performance ADCs, and reduce the production test time and cost for medium and low resolution ADCs

The bottleneck of DAC testing is the fast and accurate measurement devices. Production testing of high-resolution DACs with gigahertz clock rates is a challenging problem, and there is no widely adopted approach for on-chip testing of precision DACs in an SoC system. This work presents a new approach for testing high-resolution DACs. High speed data acquisition is achieved with flash ADCs; sufficient resolution is provided by dithering; and high test accuracy is guaranteed by the proposed data processing algorithm. This method provides a potential solution to both the production and on-chip DAC testing problems. Simulation results show that the static linearity of 14 bit DACs can be tested to better than 1 LSB accuracy, and dynamic performance of more than 85 dB SFDR can be tested with 1 dB accuracy, using 6-bit ADCs and dithering. Experimental results included in the paper also affirm the performance of the algorithm in testing high-resolution DACs using 6-bit ADCs

This work describes a linearity test strategy for ADCs that uses stimuli with precision much lower than the ADC resolution and tolerates environment nonstationarity. This approach can be applied to testing ADCs of very high performance, such as 16-bit or higher resolutions and more than 1 MSPS sampling rates, to which there is hardly a well-established solution for full-code test. Simulation and experimental results show that a 16-bit ADC can be tested to 1-LSB accuracy by using input signals of 7-bit linearity in an environment with more than 100 ppm per minute nonstationarity. The proposed method can also help control the cost of ADC production test, extend the test coverage and enable built-in self-test and test-based self-calibration.

As the performance of Analog-to-Digital Converters continues to improve, it is becoming more challenging and costly to develop sufficiently fast and low-drift signal generators that are adequately more linear than the ADC for the purpose of linearity testing. This work relaxes the linearity requirements on the signal generators used for ADC testing by alternatively employing multiple non-linear inputs. Assuming minimal prior knowledge of the input non-linearity, a testing methodology is introduced that is based upon first identifying and computationally removing the source non-linearity and then accurately estimating the ADC linearity. Production test hardware is used for validating the performance of this testing methodology using a high performance 16-bit SAR ADC as a test vehicle. Integral linearity error readings are identified to well within the +/-2 LSB range of the device specification by using only 8-bit linear inputs. This approach provides an enabling technology for costeffective full-code testing of high performance ADCs in production test and for a cost-effective implementation of built-in self-test (BIST).

A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear than the Device-Under-Test (DUT), the proposed approach can work with stimuli that are several bits less linear than the DUT. This dramatically reduces the requirements on stimulus generation for BIST applications and offers potential for using inexpensive signal generators in production test, or for testing DUTs that have a linearity performance exceeding that of the available test equipment. As a proof of concept, a histogram-based algorithm for linearity testing for Analog-to-Digital Converters (ADCs) has been proposed. It can estimate the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) of an n -bit ADC by using a ramp signal of much less than n -bit linearity and a shifted version of the same nonlinear ramp as excitation. The performance of the algorithm is comparable to that of the traditional method which uses ( n + 3)-bits or a decade more linear input signals. Complete algorithm description, extensive simulation results and experimental results obtained from using a production tester on commercially available ICs are presented to validate the potential of this algorithm.