Deyuan Xiao

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dblp:31/2362 · DBLP profile ↗

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2ranked-venue papers

1as first author

0since 2021 · last 2009

0009-0006-7312-6247ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

2 papers

Integrated circuit design · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Integrated circuit design › semiconductor device fabrication CMOS technology	0.1	1	2009	Challenges of 22 nm and beyond CMOS technology · Sci. China Ser. F Inf. Sci. 2009
Integrated circuit design technology scaling	0.1	1	2009	Challenges of 22 nm and beyond CMOS technology · Sci. China Ser. F Inf. Sci. 2009
Integrated circuit design › semiconductor devices › multi-gate devices dual-gate transistor	0.1	1	2008	Planar split dual gate MOSFET · Sci. China Ser. F Inf. Sci. 2008
Integrated circuit design › semiconductor devices › field-effect transistor MOSFET	0.1	1	2008	Planar split dual gate MOSFET · Sci. China Ser. F Inf. Sci. 2008
Integrated circuit design › semiconductor devices › device scaling CMOS scaling limits	0.0	1	2009	Challenges of 22 nm and beyond CMOS technology · Sci. China Ser. F Inf. Sci. 2009
Integrated circuit design low-power circuit design	0.0	1	2008	Planar split dual gate MOSFET · Sci. China Ser. F Inf. Sci. 2008

Methods — techniques the papers use, named apart from their topics

survey · 0.1

Year	Publication	Venue	Position
2009	Challenges of 22 nm and beyond CMOS technology Ru Huang 0001, HanMing Wu, Jinfeng Kang, Deyuan Xiao, XueLong Shi, Xia An, Runsheng Wang, Xing Zhang 0002, Yangyuan Wang	Sci. China Ser. F Inf. Sci.	4
2008	Planar split dual gate MOSFET Deyuan Xiao, Gary Chen, Roger Lee, Yung Liu, ChiCheong Shen	Sci. China Ser. F Inf. Sci.	1