Addresses a key issue that arises when attaching storage devices directly to IP networks: the perceived need for hardware acceleration of the TCP/IP networking stack. While many implicitly assume that acceleration is required, the evidence shows that this conclusion is not well-founded. In the past, network accelerators have had mixed success, and the current economic justification for hardware acceleration is poor, given the low cost of host CPU cycles. The I/O load for many applications is dominated by disk latency, not transfer rate, and hardware protocol accelerators have little effect on the I/O performance in these environments. Application benchmarks were run on an IP storage subsystem to measure performance and CPU utilization on e-mail, database, file serving and backup applications. The results show that good performance can be obtained without protocol acceleration.

Abstract This paper will center on analysis of the performance characteristics of ServerNet topologies, concentrating on the prediction, through simulation and statistical analysis, of the maximum two-way delivery time, the identification of congested links (hot spots) and tree saturation. ServerNetTM, developed by Tandem Computers Inc., is a wormhole-routed, packet-switched, point-to-point network, with special attention paid to reducing latency and to assuring reliability. ServerNet uses multiple high-speed, low-cost routers to rapidly switch data directly between data sources and destinations. The maximum two-way delivery time is necessary for determining the values of timeout counters, which are relevant to the fault-tolerant aspect of the system, and the QoS guarantees. Hot spots may cause the occurrence of tree saturation in the network i.e., where an individual tree will become congested (tree saturation) while all other trees are mostly idle, which leads to significant performance degradation. Our study is based on data generated by a simulation tool. Statistical analysis and inference methods were used to process the samples generated by the simulator and to obtain estimates for the maximum two-way packet delivery time. These methods were also used to determine the number of the samples that were required to produce estimates of the desired accuracy. Both the degree of confidence and the percentage of packets are determined by the number of samples generated by the simulator. This allows us to control the quality and accuracy of the estimate to suit our needs. Link usage statistics were recorded by the simulator for the purpose of performing a detailed investigation of congestion effects and hot spots. The study of the static and dynamic link usage statistics revealed that the extreme values of the two-way maximum delivery time were caused by links operating under heavy traffic loads and that under certain traffic patterns a tree saturation effect occurs.

In this article we introduce and evaluate a method for optimizing the router arbitration policy in point-to-point networks. These networks use multiple high-speed, low-cost routers to rapidly switch data directly between data sources and destinations. We assume that routers use an arbitration algorithm that has the ability to assign different priorities to different links thus controlling the distribution of available bandwidth among channels. We propose an analytical method that allows us to determine the correct priorities for channels so as to achieve fair arbitration thus minimizing latency, increasing throughput and eliminating tree saturation. In our study we used data generated by a simulation tool to validate the proposed analytical model for determining the weights (priorities) of router ports and to evaluate the resulting performance improvements. Link usage statistics were recorded by the simulator for the purpose of performing a detailed investigation on congestion effects particularly tree saturation. The method was applied to the ServerNet™ System Area Network (SAN), developed by Tandem Computers Inc.

This paper describes the architecture for issuing multiple instructions per clock in the NonStop Cyclone Processor. Pairs of instructions are fetched and decoded by a dual two-stage prefetch pipeline and passed to a dual six-stage pipeline for execution. Dynamic branch prediction is used to reduce branch penalties. A unique microcode routine for each pair is stored in the large duplexed control store. The microcode controls parallel data paths optimized for executing the most frequent instruction pairs. Other features of the architecture include cache support for unaligned double-precision accesses, a virtually-addressed main memory, and a novel precise exception mechanism.

article Free Access Share on An architecture for high volume transaction processing Authors: Robert W. Horst Tandem Computers Incorporated - 19333 Vallco Parkway - Cupertino, CA Tandem Computers Incorporated - 19333 Vallco Parkway - Cupertino, CAView Profile , Timothy C. K. Chou Tandem Computers Incorporated - 19333 Vallco Parkway - Cupertino, CA Tandem Computers Incorporated - 19333 Vallco Parkway - Cupertino, CAView Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 13Issue 3June 1985 pp 240–245https://doi.org/10.1145/327070.327226Published:01 June 1985Publication History 10citation459DownloadsMetricsTotal Citations10Total Downloads459Last 12 Months100Last 6 weeks25 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF