With the continuous scaling of advanced integrated circuits, thermal management has emerged as a critical design challenge due to increasing power densities and structural complexity. To ensure system reliability, especially during the sign-off stage, thermal simulation tools must provide both high spatial resolution and computational efficiency. In this work, we present ThPA, a high-performance thermal simulation framework based on finite-difference discretization and an efficient fine-grained iterative solver. ThPA leverages an aggregation-based algebraic multigrid (AgAMG) preconditioned conjugate gradient (PCG) solver, which incorporates a novel double pairing aggregation strategy to reduce AgAMG setup overhead and accelerates convergence using Krylov-subspacebased multigrid cycles as the preconditioner. Experimental results show that ThPA achieves a speedup of up to $83 \times$ over commercial solvers, while maintaining a mean absolute temperature difference below $0.08^{\circ} \mathrm{C}$ and a root-mean-square temperature difference under $0.11^{\circ} \mathrm{C}$. These results validate the effectiveness of ThPA as a fast and accurate simulator for advanced IC design.

As the power density and complexity of modern chips continue to increase, thermal analysis has become an essential step in the design process. While existing analytical approaches assume purely vertical heat flow, lateral heat transfer becomes significant when chip thickness increases, as in 3D ICs, and cooling capability is limited, as in mobile devices. Though commercial numerical tools can capture these effects, they are too computationally intensive for use in early design stages.This work proposes FALCON-3D, a high-performance and full-chip analytical thermal solver tailored for early-stage design analysis, which explicitly models lateral surface heat transfer. Experimental results demonstrate not only the computational efficiency of FALCON-3D but also that ignoring lateral heat transfer introduces notable errors in temperature prediction, underscoring the importance of incorporating lateral effects.

This work develops an efficient thermal-aware chiplet placer with sequence-pair representation. It provides wirelength-driven placement and thermal-aware placement. Its wirelength-driven option combines the sequence-pair based tree, a parallel branch-and-bound method and advanced placement/pruning techniques to efficiently find the minimum-wirelength placement. The thermal-aware option incorporates the wirelength-driven option with a thermal-aware net weight decision method and a post chiplet placement procedure to effectively make a tradeoff between wirelength and temperatures of chiplets. Compared with the state-of-the-art wirelength-driven chiplet placer, the developed wirelength-driven chiplet placer not only finds the same or less minimum wirelength placement but also speeds up at most two orders of magnitude. With considering thermal effect, Its thermal-aware option can reduce the maximum temperature up to 9.4 ℃ with an average 4.7% increase of wirelength, while ensuring that all cases meet thermal constraints. Compared to the state-of-the-art thermal-aware chiplet placer, the proposed thermal-aware placer not only takes shorter runtime but also provides less total wirelength placement.

This work develops an efficient chiplet placer with thermal consideration for 2.5D ICs. Combining the sequence-pair based tree, branch-and-bound method, and advanced placement/pruning techniques, the developed placer can find the solution fast with the optimized total wirelength (TWL) on half-perimeter wirelength (HPWL). Additionally, with the post placement procedure, the placer reduces maximum temperatures with slight increase of wirelength. Experimental results show that the placer can not only find better optimized TWL (reducing 1.035% HPWL) but also speed up at most two orders of magnitude than the prior art. With thermal consideration, the placer can reduce the maximum temperature up to 8.214 °C with an average 5.376% increase of TWL.

This work utilizes the XGBoost to build a machine-learning-based IR drop predictor, XGBIR, for the power grid. To capture the behavior of power grid, we extract its several features and employ its locality property to save the extraction time. XGBIR can be effectively applied to large designs and the average error of predicted IR drops is less than 6 mV.

This work presents a system-level thermal simulator, Phone-nomenon, to predict the thermal behavior of smartphone. First, we study the nonlinearity of internal and external heat transfer mechanisms and propose a compact thermal model. After that, we develop an iterative framework to handle the nonlinearity. Compared with a commercial tool, ANSYS Icepak, Phonenomenon can achieve two and three orders of magnitude speedup with 3.58% maximum error and 1.72°C difference for steady-state and transient-state simulations, respectively. Meanwhile, Phone-nomenon also fits the measured data of a built thermal test vehicle pretty well.

Heat pipe is an effective passive cooling technique for mobile devices. This work builds a multi-angle bended heat pipe thermal model and presents an X-architecture routing engine guided by developed dynamic thermal weights to construct the heat pipe path for reducing the operating temperatures of a smartphone. Compared with a commercial tool, the error of the thermal model is only 4.79%. The routing engine can efficiently reduce the operating temperatures of application processors at least 13.20% in smartphones.

During package manufacturing process, open defects of power bumps may cause insufficient power supply and degrade the power network yield. This work presents a redundant power bump insertion method to ensure power integrity by considering the power bump yields. The proposed method can efficiently assign redundant bumps by accurately estimating the location of worst load yield and minimizing the amounts of redundant bumps to enhance the power network yield.

While the performance of smartphones becomes much higher, the application processor consumes considerable power. Thus, it is hard to meet thermal constraints by using conventional cooling techniques. Fortunately, since heat pipes can efficiently transfer the thermal energy from hot regions to cool regions, temperatures in hot regions can be reduced greatly. Hence, in the past three years, the heat pipe cooling techniques have been applied to smartphones by industries. However, although the time-consuming commercial simulation tools, such as ANSYS Fluent, can provide accurate thermal maps, they may lead to inefficiency during design stages. Besides, the compact thermal model for bended heat pipes is still underdeveloped. Therefore, efficient thermal simulation for smartphones with bended heat pipes should be developed for the design stage. Furthermore, the routing of bended heat pipe should be optimized to obtain more thermal energy transfer.

Effective transient power grid simulators are needed during design processes because a designed power grid needs to be numerously analyzed. This paper builds an efficient and reliable incremental power grid transient simulator, which we name it InTraSim, by integrating macro modeling techniques, sparse recovery mechanisms, an innovated pseudo-node value estimation method, and an initiated adaptive error control scheme. InTraSim is able to deal with not only element-value alterations of designs but also topology modifications of designs.

Through-silicon-via (TSV)-to-TSV coupling issue can degrade the signal integrity in 3-D integrated circuit designs. This paper develops a 3-D partitioning-based force-directed placer, NaPer, to reduce the total coupling noise between TSVs and alleviate the maximum coupling noise between them. We introduce two denoise forces: TSV decoupling force and TSV density force. The TSV decoupling force is determined by the coupling noise between TSVs for separating strong coupling TSVs, and the TSV density force is determined by the TSV density for evenly distributing TSVs. The experimental results show that NaPer can effectively reduce 15.0% total TSV coupling noise and 42.7% maximum TSV coupling noise on average with only 4.5% wirelength overhead. Besides, NaPer also shows great performance in wirelength that is competitive to the state-of-the-art 3-D placer.

To sustain Moore's law, three-dimensional integrated circuit (3-D IC) is a promising solution to achieve high performance and low cost targets. However, its operating temperature is higher than that of a 2-D IC because of its high power density of stacked dies and ill of heat dissipation capability. Therefore, on-chip thermal effects have become major concerns of 3-D ICs. Utilizing look-up table approach, this paper, LUTSim, provides two thermal simulation engines, I-LUTSim and S-LUTSim, to efficiently calculate the thermal profile of a 3-D IC. I-LUTSim is suitable for full-chip thermal analysis, and S-LUTSim is suited for incremental-thermal updating. With utilizing the prebuilt tables, compared with a commercial tool ANSYS, the absolute error of I-LUTSim is less than 0.29%. Moreover, with negligible loss of accuracy, I-LUTSim can be 38.8 times faster than a well-known matrix solver SuperLU for performing full-chip thermal simulation. Besides, S-LUTSim can be over 1.05 million times faster than SuperLU for adjusting the thermal profile after inserting/removing a through silicon via.

The power grid needs to be frequently analyzed during the design process of power distribution network. Hence, an effective method being able to capture its transient behavior is desired for designers.

This work presents an iterative look-up table based thermal simulator, I-LUTSim, to efficiently estimate the temperature profile of three-dimensional integrated circuits. I-LUTSim includes two stages. First, the pre-process stage constructs thermal impulse response tables. Then, the simulation stage iteratively calculates the temperature profile via the table lookup. With this two-stage scheme, the maximum absolute error of I-LUTSim is less than 0.41% compared with that of a commercial tool ANSYS. Moreover, I-LUTSim is at least an order of magnitude faster than a fast matrix solver SuperLU [1] for the full-chip temperature simulation.

By combining analytical and numerical simulation techniques, this work develops a hybrid thermal simulator, NUMANA, which can effectively deal with complicated material structures, to estimate the temperature profile of a 3-D IC. Compared with a commercial tool, ANSYS, its maximum relative error is only 1.84%. Compared with a well known linear system solver, SuperLU [1], it can achieve orders of magnitude speedup.

This work provides an efficient statistical electrothermal simulator for analyzing on-chip thermal reliability under process variations. Using the collocation-based statistical modeling technique, first, the statistical interpolation polynomial for on-chip temperature distribution can be obtained by performing deterministic electrothermal simulation very few times and by utilizing polynomial interpolation. After that, the proposed simulator not only provides the mean and standard deviation profiles of on-chip temperature distribution, but also innovates the concept of thermal yield profile to statistically characterize the on-chip temperature distribution more precisely, and builds an efficient technique for estimating this figure of merit. Moreover, a mixed-mesh strategy is presented to further enhance the efficiency of the developed statistical electrothermal simulator. Experimental results demonstrate that (1) the developed statistical electrothermal simulator can obtain accurate approximations with orders of magnitude speedup over the Monte Carlo method; (2) comparing with a well-known cumulative distribution function estimation method, APEX [Li et al. 2004], the developed statistical electrothermal simulator can achieve 215× speedup with better accuracy; (3) the developed mixed-mesh strategy can achieve an order of magnitude faster over our baseline algorithm and still maintain an acceptable accuracy level.

This work introduces the concept of thermal yield profile for the hot-spot identification with considering process variations and provides an efficient estimating technique for the thermal yield profile. After executing a mixed-mesh strategy for generating statistical polynomial expression of the on-chip temperature distribution, the thermal yield profile is obtained by a skew-normal based moment matching technique. Comparing with the Monte Carlo method, experimental results demonstrate that our method can efficiently and accurately estimate the thermal yield profile. With the same level of accuracy, our skew-normal based method achieves 215x speedup over the state of the art, APEX [1], for estimating the thermal yield profile. Moreover, results show that our mixed-mesh statistical polynomial expression generator achieves 130x speedup over the statistical collocation based method [2] and still accurately estimates the thermal yield profile.

In this work, a hierarchical bin-based legalization approach, HiBinLegalizer, is developed to legalize standard cells with minimal movement. First, a chip is divided into several bins with equal size. Then, starting with the most crowed unlegalized bin, a merging procedure for bins is used to integrate bins into a cross-shape region or a square-shape region until the cell density in that region is less than a specific cell-density-threshold. After that, an efficient legalization method which simultaneously preserves the cell orders in each row and minimizes the weighted sum of movement distances is developed to legalize cells in that region to limit the movable scope. To improve the legalization quality, HiBinLegalizer refreshes the positions of legalized cells during legalization. The legalizing procedure is repeated until all cells are non-overlapped. Compared with the state-of-the-art method, Abacus, HiBin-Legalizer can reduce the total movement of cells to be 48% in average and save the largest movement of cells to be 140% in average. Moreover, HiBinLegalizer can reduce the HPWL by 47% and obtain average 1.11x runtime speed up.

In this work, we develop a statistical thermal simulator including the effect of spatial correlation under within-die process variations. This method utilizes the Karhunen-Loève (KL) expansion to model the physical parameters, and apply the Polynomial Chaoses (PCs) and the stochastic Galerkin method to tackle stochastic heat transfer equations. We demonstrate the accuracy and efficiency of our simulator by comparing with the Monte Carlo simulation, and point out that the stochastic thermal analysis is essential to provide a robust estimation of temperature distribution for the thermal-aware design flow.

Redundant via insertion is a widely recommended technique to enhance the via yield and reliability. In this paper, the post-routing redundant via insertion problem is transformed to a mixed bipartite-conflict graph matching problem, and an efficient heuristic minimum weighted matching (HMWM) algorithm is presented to solve it. The developed method not only inserts redundant vias for alive vias but also protects the dead vias by utilizing the wire spreading capability- that's to say, the method shifts wires into the empty space and adds redundant vias for dead vias to further enhance the via yield. Experimental results show that the average insertion rate of alive vias is 99.54% with a short run time, and the wire spreading technique can achieve average insertion rate to be 54.41% for dead vias.

In this paper, a grid-based multiple supply voltage (MSV) assignment method is presented to statistically minimize the total power consumption of 3-D IC. This method consists of a statistical electro-thermal simulator to get the mean and variance of on-chip, a thermal-aware statistical static timing analysis (SSTA) to take into account the thermal effect on circuit timing, the statistical power delay sensitivity-slack product to be the optimization criterion, and an incremental update of statistical timing to save the runtime. The experimental results demonstrate the effectiveness of the developed methodology and indicate that the consideration of the thermal effect in the circuit simulation is imperative.

The capability of predicting the temperature profile is critically important for timing estimation, leakage reduction, power estimation, hotspot avoidance and reliability concerns during modern IC design. This paper presents an accurate and fast analytical full-chip thermal simulator for early-stage temperature-aware chip design. By using the generalized integral transforms (GIT), an accurate formulation is derived to estimate the temperature distribution of full-chip with a truncated set of spatial bases which only needs very small truncation points. Then, we develop a fast Fourier transform like evaluating algorithm to efficiently evaluate the derived formulation. Experimental results confirm that the proposed GIT-based analyzer can achieve an order of magnitude speedup compared with a highly efficient Green's function-based thermal simulator. Finally, we propose a 3-D IC thermal simulator and demonstrate its efficiency and accuracy.

The capability of predicting the temperature profile is critically important for circuit timing estimation, leakage reduction, power estimation, hotspot avoidance, and reliability concerns during modern IC designs. This paper presents an accurate and fast analytical full-chip thermal simulator for the early-stage temperature-aware chip design. By using the technique of generalized integral transforms (GIT), our proposed method can accurately estimate the temperature distribution of full-chip with very small truncation points of bases in the spatial domain. We also develop a fast Fourier transform (FFT) like evaluating algorithm to efficiently evaluate the temperature distribution. Experimental results confirm that our GIT based analyzer can achieve an order of magnitude speedup compared with a highly efficient Green's function based method.

The soaring clocking frequency and integration density demand robust and stable power delivery to support tens of millions of transistor switching. In this paper, we consider the problem of minimizing the area of wires and decoupling capacitors (decaps) for a power delivery network, subject to the limit on integral of voltage drops. First, we derive the gradients of constraint function without Tellegen's theorem. This greatly simplifies the discuss of adjoint sensitivity analysis. Then, we apply the IEKS method to speed up the sensitivity analysis over 3 times. Finally, this efficient analyzer is incorporated with the state-of-the-art nonlinear programming package, SNOPT, to perform the optimization. Extensive experimental results show that the proposed method can work efficiently for large power delivery networks.

This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we develop and apply the IEKS (Improved Extended Krylov Subspace) method to build the multiport Norton equivalent circuits which transform all the internal sources to Norton current sources at ports. Since there are no active elements inside the Norton circuits, passive or realizable model order reduction techniques such as PRIMA can be applied. The significant speed improvement, 700 times faster than Spice with less than 0.2% error and 7 times faster than a state-of-the-art solver, InductWise, is observed. To further reduce the top-level hierarchy runtime, we develop a second-level model reduction algorithm and prove its passivity.

Abstract — In this paper, we propose a novel hierarchical analysis methodology to facilitate efficient chip-level power fluctuation analysis. With extreme efficiency and simplicity, our design methodology first builds time-varying multiport Norton equivalent circuits in a row-by-row or block-by-block based followed by global analysis on the integrated reduced models. After generating the Norton equivalent sources at external ports, we apply realizable model order reduction technologies to further reduce model. Since the elements of our reduced model are also RC devices, they are fully compatible with general circuit simulation engines. The experimental results demonstrate more than 4X speed up with the flat simulation while maintaining within 5 % of accuracy. I.

Recent studies show that the nonuniform thermal distribution on the substrate and interconnects has impact on the circuit reliability and performance. Hence three-dimensional (3-D) thermal analysis is crucial to analyze these effects. In this paper, we present and develop an efficient 3-D transient thermal simulator based on the alternating direction implicit (ADI) method for large scale temperature estimation problems. Our simulator, 3D Thermal-ADI, not only has a linear runtime and memory requirement, but also is unconditionally stable. Detailed analysis of the 3-D nonhomogeneous cases and boundary conditions for on-chip VLSI applications are introduced and presented. Extensive experimental results show that our algorithm is not only orders of magnitude faster than the traditional thermal simulation algorithms, but is also highly accurate and memory efficient. The temperature profile of steady state can be reached in few iterations. The software is avaiable on the web [1].

The rising power consumption and clock frequency of very large scale integration technology demand robust and stable power delivery. Extensive transient simulations on large-scale power delivery structures are required to analyze power delivery fluctuation caused by dynamic IR drop and Ldi/dt drop as well as package and on-chip resonance. In this paper, we develop a novel and efficient transient simulation algorithm for the power distribution networks. Our algorithm, three-dimensional (3-D) transmission-line-modeling alternating-direction-implicit (TLM-ADI) method, first models the power delivery structure as 3-D transmission line shunt-node structure and transfers those equations to the telegraph equation. Finally, we solve it by the alternating direction implicit method. The 3-D TLM-ADI method, with linear runtime and memory requirement, is also unconditionally stable, which ensures that the time steps are not limited by any stability requirement. Extensive numerical simulation results show that the proposed algorithm is not only over 300 000 times faster than SPICE but also extremely memory saving and accurate.

This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we develop and apply the IEKS (Improved Extended Krylov Subspace) method to build the Multi-port Norton Equivalent circuits which transform all the internal sources to Norton current sources at ports. Since there is no active elements inside the Norton circuits, passive or realizable model order reduction techniques such as PRIMA can be applied. To further reduce the top-level hierarchy runtime, we develop a second-level model reduction algorithm and prove its passivity. Experimental results show 400-700X runtime improvement with less than 0.2% error.

The soaring clocking frequency and integration density demand robust and stable power delivery to support tens of millions of transistors switching. To ensure the design quality of power delivery, extensive transient power grid simulations need to be performed during the design process. However, the traditional circuit simulation engines are not scaled well for the complexity of power delivery. As a result, it often takes a long runtime and huge memory requirement to simulate a medium-sized power grid circuit. In this paper, the authors develop and present a new efficient transient simulation algorithm for power distribution. The proposed. algorithm, transmission-line-modeling alternating-direction-implicit (TLM-ADI), first models the power delivery structure as transmission line mesh structure, then solves the transient modified nodal analysis matrices by the alternating-direction-implicit method. The proposed algorithm, with linear runtime and memory requirement, is also unconditionally stable which ensures that the time-step is not limited by any stability requirement. Extensive experimental, results show that the proposed algorithm is not only orders of magnitude faster than SPICE but also extremely memory saving and accurate.

Clock-tuning has been classified as important but tough tasks due to the non-convex nature caused by the skew requirements. As a result, all existing mathematical programming approaches are often trapped at local minimum and have no guarantee of obtaining global optimal solution. In this paper, we present optimal clock tuning algorithms which effectively apply capacitance-padding to reduce clock skew, power, and delay for general clock topologies. Capacitance-padding can be achieved by wire-spacing, wire-splitting, wire-padding and transistor-padding. We show that under the El-more delay model, capacitance-padding can be formulated as a linear programming problem and solved with great efficiency. Capacitance-padding can also be used as a post processing step for any non-zero-skew clock tree or mesh structure to achieve timing closure. Experiment results on several practical industry examples show that our algorithms are extremely efficient. Problems with over 6000 variables can be optimally tuned within 1 minute on a PC with 500 -MHZ Intel Pentium III processor.

Article Share on Hierarchical model order reduction for signal-integrity interconnect synthesis Authors: Yu-Min Lee Department of Electrical and Computer Engineering, University of Wisconsin at Madison, Madison, WI Department of Electrical and Computer Engineering, University of Wisconsin at Madison, Madison, WIView Profile , Charlie Chung-Ping Chen Department of Electrical and Computer Engineering, University of Wisconsin at Madison, Madison, WI Department of Electrical and Computer Engineering, University of Wisconsin at Madison, Madison, WIView Profile Authors Info & Claims GLSVLSI '01: Proceedings of the 11th Great Lakes symposium on VLSIMarch 2001Pages 109–114https://doi.org/10.1145/368122.368883Published:01 March 2001Publication History 3citation178DownloadsMetricsTotal Citations3Total Downloads178Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Publisher SiteGet Access

The soaring clocking frequency and integration density demand robust and stable power delivery to support tens of millions of transistors switching. To ensure the design quality of power delivery, extensive transient power grid simulations need to be performed during design process. However, the traditional circuit simulation engines are not scaled as well as the complexity of power delivery, as a result, it often takes a long runtime and huge memory requirement to simulate a medium size power grid circuit. We develop and present a new efficient transient simulation algorithm for power distribution. The proposed algorithm, TLM-ADI (transmission-line-modeling alternatingdirection-implicit), first models the power delivery structure as transmission line mesh structure, then solves the transient MNA matrices by the alternating-direction-implicit method. The proposed algorithm, with linear runtime and memory requirement, is also unconditionally stable which ensures that the time-step is not limited by any stability requirement. Extensive experimental results show that the proposed algorithm is not only orders of magnitude faster than SPICE but also extremely accurate.

Hierarchical capacitance extraction algorithms have been shown an efficient and accurate capacitance extraction algorithm. An improved algorithm is also proposed to remove its runtime dependency on the number of conductors by a combination of hierarchical and multipole expansion algorithm. In this paper, we show that with the introduction of hierarchical merging operation and super-node representation, we can achieve linear runtime and accuracy without involving multipole expansion. Experimental results show over 10/spl times/ runtime improvement and 20/spl times/ memory saving over the multipole approaches with comparable accuracy and better numerical stability.