The power optimization of mixed polarity Reed–Muller (MPRM) logic circuits is a classic combinatorial optimization problem. Existing optimization approaches often suffer from slow convergence and a propensity to converge to local optima, limiting their effectiveness in achieving optimal power efficiency. First, we propose a novel multi-strategy fusion memetic algorithm (MFMA). MFMA integrates global exploration via the chimp optimization algorithm with local exploration using the coati optimization algorithm based on the optimal position learning and adaptive weight factor (COA-OLA), complemented by population management through truncation selection. Second, leveraging MFMA, we propose a power optimization approach for MPRM logic circuits that searches for the best polarity configuration to minimize circuit power. Experimental results based on Microelectronics Center of North Carolina (MCNC) benchmark circuits demonstrate significant improvements over existing power optimization approaches. MFMA achieves a maximum power saving rate of 72.30% and an average optimization rate of 43.37%; it searches for solutions faster and with higher quality, validating its effectiveness and superiority in power optimization.

Traditional logic synthesis methods are based on Boolean logic, which tends to produce redundant logic structures in dense circuit applications, such as complex number operations and error detection/correction coding. Traditional Boolean and Reed-Muller (TB-RM) logic synthesis method combining traditional Boolean (TB) logic and Reed-Muller (RM) logic can improve comprehensive optimization indexes and reduce cost. The existing TB design method is not effective when dealing with constrained systems with high-resource utilization requirements. In addition, traditional synthesis methods do not consider multiobjective optimization of area, power consumption and reliability. To solve these problems, we propose an effective dual logic synthesis method (EDSM), which includes dual logic detection method (DDM) and differential evolution algorithm based on multidimensional mutation strategy (DE-MMS). DDM can complete the logic detection function, and DE-MMS can further optimize the polarity. In addition, to evaluate the soft errors occurring more efficiently at the logic level, we propose a soft error rate (SER) estimation model. Experimental results show that compared with state-of-the-art evolutionary algorithms, EDSM can search for optimal solutions in all optimization problems; compared with commonly used TB-based minimization methods, EDSM has obvious advantages in multiobjective optimization of area, power consumption and SER. After 6-LUT FPGA technology and standard cells mapping, by selecting area as the optimal cost implementation, we obtain average improvements in the area of 14% and 2%, respectively.

The arbitrarily connected nature of IoT has led to an explosion in the number of embedded devices accessed. These devices typically store and process large amounts of private and critical data. Most of these data are transmitted in plaintext over the bus, which is vulnerable to attacks such as theft, leakage, tampering, and even control flow hijacking. Encryption and authentication of memory data can effectively alleviate these problems. Existing solutions introduce significant performance overhead while providing data protection. Therefore, in this article, we propose a low-latency, high-performance transparent memory data encryption and authentication hardware protection scheme based on Ascon-128, in which the multistage pipeline design and the optimization of address labels effectively reduce the encryption/decryption latency and the size and storage overhead of nonce data. Based on the designed hardware architecture, the performance overhead introduced is evaluated in terms of bandwidth, latency, runtime, and score using multiple test programs on a CVA6-32-bit RISC-V SoC platform. The measured results from TinyMemBench demonstrate that the memory read and write bandwidth introduced by the proposed transparent memory data encryption and authentication scheme is reduced by 10.2% and 5.6%, respectively. For real intensive computational loads, the average runtime of Crystal-Dilithium and Crystal-Kyber increases by 6.32% and 6.42%, respectively, under three different parameter sets.

Power optimization can reduce heat dissipation costs and has become an important step of circuit logic synthesis. Because the power optimization for mixed polarity Reed–Muller (MPRM) circuits is a combinatorial optimization problem, in this paper, we first propose a multilevel adaptive memetic algorithm (MAMA), which includes global exploration optimizer, local heuristic optimizer, and initial population optimizer. We use the proposed differential evolution optimization, simulated annealing optimization, and data matching algorithm to make the population evolve. Moreover, based on the proposed matrix decomposition strategy and parallel polarity conversion algorithm, we propose a power optimization approach (POA) for MPRM circuits, which searches for an MPRM circuit with a minimum power using the MAMA. Experimental results demonstrated the effectiveness and superiority of the POA in optimizing the power of MPRM circuits.

Area optimization is one of the most important contents of circuits logic synthesis. The smaller area has stronger testability and lower cost. However, searching for a circuit with the smallest area in a large-scale space of polarity is a combinatorial optimization problem. The existing optimization approaches are inefficient and do not consider the time cost. In this paper, we propose a multi-strategy wolf pack algorithm (MWPA) to solve high-dimension combinatorial optimization problems. MWPA performs global search based on the proposed global exploration strategy, extends the search area based on the Levy flight strategy, and performs local search based on the proposed deep exploitation strategy. In addition, we propose a fast area optimization approach (FAOA) for fixed polarity Reed-Muller (FPRM) logic circuits based on MWPA, which searches the best polarity corresponding to a FPRM circuit. The experimental results confirm that FAOA is highly effective and can be used as a promising EDA tool.

As the Internet of Things (IoT) expands explosively existing network connections, the transmission and processing of private data is facing more serious threats of leakage and theft. Classical public key encryption schemes are difficult to guarantee strong security protection, because the mathematically hard problems they rely on are no longer difficult to solve under the rapid development of quantum computing. Therefore, a more high-performance and quantum-resistant encryption scheme Ring-ExpLWE is proposed, in which the error vector is sampled in the exponential distribution instead of the binary distribution in the previous Ring-BinLWE. We evaluate the Ring-ExpLWE’s security level by analyzing the runtime under quantum hybrid attack and comparing the standard deviation of the noise polynomial coefficients. Compared with Ring-BinLWE, the proposed Ring-ExpLWE requires larger runtime for quantum hybrid attack and has a more discrete noise distribution. Therefore, Ring-ExpLWE can provide a higher security level under the same parameter set. Moreover, the high-performance software and hardware implementations for the Ring-ExpLWE scheme are proposed, respectively. Based on the Cortex-M3 microprocessor platform, encryption, and decryption only require 35.6 and 17.8 ms in our software implementation, respectively. Compared with the previous Ring-BinLWE schemes, while significantly improving the security level, the Area$\times $Time (AT) of our high-performance and lightweight hardware implementations is reduced by 49.2% and 49.5%, respectively, when the FPGA platform is Spartan 6.

With the emergence of the multicore architecture and the increase of chip operating frequency, power optimization has become a key step of circuit logic synthesis. Aiming at the XNOR/OR circuits, with the goal of minimizing power, construct the optimal polarity fixed-polarity Reed–Muller (FPRM) circuits power optimization scheme. However, the power optimization for FPRM circuits is a multipeak combinatorial optimization problem, we first propose a metaheuristic optimization algorithm (MOA), which includes the global exploration optimizer, local deep exploitation optimizer, and initial population and uses the proposed differential evolution optimization, fierce wolf siege algorithm-based tabu search, and improved skew tent map to make the population evolve. Based on the proposed Huffman tree construction algorithm and MOA, we propose an efficient power optimization approach (EPOA) to find the minimum power FPRM circuit. Experimental results on the benchmark circuits confirm the effectiveness of EPOA.

Learning with error (LWE) over the ring based on binary distribution (ring-BinLWE) has become a potential Internet-of-Things (IoT) confidentiality solution with its anti-quantum attack properties and uncomplicated calculations. Compared with ring-LWE based on discrete Gaussian distribution, the decryption scheme of ring-LWE based on binary distribution needs to be re- determined due to the asymmetry of the error distribution. The direct application of the ring-LWE decryption function based on discrete Gaussian distribution can cause serious misjudgment. In this article, we propose a more accurate and robust decryption scheme for ring-BinLWE based on 2’s complement ring. Compared with the previous decryption function, the re- derived decryption function significantly improves the decoding rate by 50%. Furthermore, based on the proposed decryption function, high-performance, and lightweight hardware architectures for terminal devices in IoT are, respectively, proposed, which are scalable and can be easily adapted to ring-BinLWE hardware deployment with other parameter sets. When the parameter set is$n\,\,=$256,$q\,\,=$256, the high-performance implementation consumes 7.6k LUTs, 6.2k FFs, and 2.3k SLICEs on Spartan 6 field-programmable gate array (FPGA) platform. Compared with the previous implementation, our resource overhead increases by only 23% while the decryption accuracy is significantly improved by 50%. The lightweight implementation for parameter set$n\,\,=$256,$q\,\,=$256 consumes only 230 LUTs, 338 FFs, and 84 SLICEs on the Spartan 6 FPGA platform. Compared with the previous work, the area$\times $time (AT) is reduced by 47.8%, which is more suitable for deployment on resource-constrained IoT nodes.

Delay optimization has now emerged as an important optimization goal in logic synthesis. The delay optimization for ternary fixed polarity Reed–Muller (FPRM) circuits aims to find a ternary FPRM circuit with a minimum delay. Because the delay optimization for ternary FPRM circuits is a combinatorial optimization problem, in this paper, we first propose a multilevel adaptive quantum genetic algorithm (MAQGA), which divides individuals into three-level populations: high-level population, intermediate-level population, and low-level population and uses the proposed ternary quantum rotation gate, proposed ternary quantum correction gate, and proposed multi-operator adaptive mutation mechanism to make the three-level populations evolve. Moreover, based on the proposed delay decomposition strategy, we propose a delay optimization approach (DOA) for ternary FPRM circuits under the unit delay model, which searches for a ternary FPRM circuit with a minimum delay using the MAQGA. Experimental results demonstrated the effectiveness and superiority of the DOA in optimizing the delay of ternary FPRM circuits.

Recently, extensive research attention has been drawn to the program executing security of embedded processor since increasing code tamper attacks, as well as transient faults severely affect the safety of embedded systems. The security monitoring and fault recovery technique is one of the effective methods to ensure the security and performance of embedded devices. In this article, an architecture for the security monitoring and fault recovery is proposed for run-time program execution, which builds a Monitoring Cache (M-Cache) and then checks the integrity based on reference data. Especially, the proposed architecture will build the checkpoint once the M-Cache is missed and also take the rollback operation after the unsuccessful of integrity check. In addition, three tampered positions (e.g., instruction register within the pipeline, instruction within the cache, and code within memory) have been elaborately focused on to guarantee the normal running of the embedded system. Eventually, by adopting the open RISC processor for algorithm implementation and verification, the proposal has been proven to be promising for the detection of a fault or tampered program, as well as the fast recovery of running environment and code.

Fixed polarity Reed-Muller expressions (FPRMs) are well-suited for many practical applications due to they have many excellent properties. In order to obtain an optimal FPRM with fewest product terms, we propose an efficient minimization algorithm (EMA-FPRMs) for FPRMs. The main idea behind the EMA-FPRMs is that, firstly, the incompletely specified Boolean function is transformed into the zero polarity incompletely specified fixed polarity RM expression (ISFPRM) by using the proposed ISFPRM acquisition algorithm; secondly, the polarity and allocation of don't care terms of ISFPRM is encoded as chromosome; lastly, the optimal FPRM with fewest product terms is obtained by using genetic algorithm (GA), in which the FPRM that corresponds to the given chromosome is obtained by using the proposed chromosome conversion algorithm. The experimental results on MCNC benchmark circuits show that compared with the traditional polarity optimization approach which neglects the don't care terms, the EMA-FPRMs is highly effective in minimizing the number of product terms of FPRMs. Moreover, the EMA-FPRMs is faster than the GA based minimization algorithm which also considers the don't care terms.

Mixed Polarity Reed-Muller (MPRM) logic draws more and more attention for its advantages over Boolean logic. This paper works on power optimization in logic synthesis for MPRM logic circuits. We present a power estimation model for MPRM logic circuits from a probabilistic point of view. A key feature of this technique is that it provides an accurate and efficient way to handle temporal signal correlations during estimation of average power by using lag-one Markov chains. Besides, an ordered binary decision diagrams-based procedure is used to propagate the temporal correlations from the primary inputs throughout the network. At last, this power estimation model is used in low power synthesis for MPRM logic circuits. This model has been evaluated in C language and a comparative analysis has been presented for many benchmark circuits. The results show that this model gives very good accuracy and does well in low power design for MPRM logic circuit.