In this paper a new 3-bit burst-error correcting code is proposed. Compared to a 1-bit error correcting Hamming code only two additional check bits are needed and compared to a 3-bit burst-error correcting Burton code the number of check bits can be reduced by 2. Since the proposed code is systematically designed by use of finite field algebra the code can be determined for an arbitrary word length and decoding is simple. Examples for different word length with up to about 1000 bits are described. The proposed code can correct single bit errors, adjacent two-bit errors, adjacent 3-bit errors and nearly adjacent 2-bit errors and may be useful for error correction in registers or register arrays, in combinational circuits and also in memories for which data-multiplexing is not used.

This paper presents a novel approach to evaluate the impact of aging mechanisms of digital circuits over their lifetimes, focusing on the analysis of measurement data. Aging of devices results in a performance reduction of digital circuits, which might result in timing violations and thus functional failure. To be able to evaluate the current timing behavior of circuits, their timing properties can be observed by in situ timing monitors. In this work, the timing slack of functional paths is extracted by in situ monitors and measured by a 5-bit time to digital converter (TDC) to accurately assess the reliability status of the circuit. Thus, aging induced performance degradation over lifetime can be monitored. By observing the timing properties of functional paths, intra-die variations of process, voltage, temperature and aging (PVTA) are monitored [1, 2]. Thus, an accurate assessment of the reliability status of the circuit is achieved.

In safety critical applications precise characterization of circuits to predict the lifetime reliability is a key challenge. This paper proposes a reliability assessment tool to model and simulate the NBTI degradation including its recovery effect during the design phase of digital circuits. The model is based on single device models and the corresponding measurement data. The circuits under test can be custom designed on transistor level and/or designed on gate level. The toolset is applied to a test circuit to evaluate its reliability within the lifetime. Considering not only the permanent component of NBTI but also the recoverable part, the tool provides a useful means to prevent an early circuit failure at minimum costs. Our studies support the applicability of the proposed method to efficiently estimate application specific reliability requirements over lifetime.

Today, modern high-end cars have close to 100 electronic control units (ECUs) that are used to implement a variety of applications ranging from safety-critical control to driver assistance and comfort-related functionalities. The total sum of these applications is several million lines of software code. The ECUs are connected to different sensors and actuators and communicate via a variety of communication buses like CAN, FlexRay and now also Ethernet. In the case of electric vehicles, both the amount and the importance of such electronics and software are even higher. Here, a number of hydraulic or pneumatic controls are replaced by corresponding software-implemented controllers in order to reduce the overall weight of the car and hence to improve its driving range. Until recently, most of the software and system design in the automotive domain -- as in many other domains -- relied on an always correctly functioning or a zero-defect hardware implementation platform. However, as the device geometries of integrated circuits continue to shrink, this assumption is increasingly not true. Incorporating large safety margins in the design process results in very pessimistic design and expensive processors. Further, the processors in cars -- in contrast to those in many consumer electronics devices like mobile phones -- are exposed to harsh environments, extreme temperature variations, and often, strong electromagnetic fields. Hence, their reliability is even more questionable and must be explicitly accounted for in all layers of design abstraction -- starting from circuit design to architecture design, to software design and runtime management and monitoring. In this paper we outline some of these issues, currently followed practices, and the challenges that lie ahead of us in the automotive and electric vehicles domain.

The proposed voltage scheme adaptively tunes the supply voltage of digital circuits, according to PVTA variations. By exploiting unused timing margin, produced by state-of-the-art worst-case designs, energy efficiency is significantly increased. In-situ delay monitoring is performed by enhanced flip-flops, observing signal delays in critical paths. We introduce a novel methodology to analyze the closed-loop behavior of the overall control scheme by a Markov approach, based on extensive transistor simulations. The digital logic and the AVS control circuitry are designed in 65nm CMOS for an image processing application. The AVS approach optimizes dynamic and leakage power dependent on the user-defined image quality requirements.

In this paper, we present an adaptive voltage scaling (AVS) scheme to tune the supply voltage of digital circuits according to variations. Compared to worst-case designs, which produce fixed and excessively large safety margins, a considerable amount of energy can be saved by this approach. The AVS technique is based on in-situ delay monitoring, i.e. observing the timing in critical paths. For this task, we propose a Pre-Error flip-flop, that is capable of detecting late data transitions - so-called pre-errors. We provide an in-depth analysis, that is based on a Markov model, to describe the closed loop voltage regulation. We simulated the power saving potential compared to the worst-case design and obtained a reduction of 13.5% in active energy for a negligible error rate of 1E-15. Moreover, we illustrate the opportunity to further reduce the power consumption when tolerating higher error rates. This way, our approach can gain the optimal power saving for a given allowed failure probability.

We present an aging analysis flow able to calculate the degraded circuit timing. To the best of our knowledge it is the first approach on gate level so far capable of analyzing the impact of the two dominant drift-related aging effects - NBTI and HCI - on complex digital circuits. The aging-aware gate model used to compute the aged circuit timing provides not just the cell delay degradation, but also the degradation of the output slope. To get more accurate results, the individual workload of a gate can be considered.

Soft error rates measured on embedded SRAMs in a 65 nm CMOS technology show a significant increase of the error rate induced by neutron radiation (NSER), while the number of soft errors due to alpha radiation (ASER) is within the expected range. In this paper it will be discussed, that the increase of the NSER values is caused by an unexpected high number of single event upsets (SEU) that flip multiple SRAM cells simultaneously (multi-bit upset). As root cause radiation induced switching of parasitic bipolar transistors was found.