EDBT 2026 Demo / reviewers in the wild / expert
Victor Luchangco
dblp:31/3102
· DBLP profile ↗
46ranked-venue papers
9as first author
1since 2021 · last 2022
0000-0002-1900-5755ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 23 · 5 first-authorSoftware engineering, systems software and programming languages · 10 · 1 first-authorTheory of computation · 7 · 1 first-authorComputer networks · 3 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
13 papers |
Concurrent programming · 58% Programming languages and type systems · 36% Program verification · 3% | |
| Computer architecture, parallel and distributed computing, and storage systems
5 papers |
Parallel and multicore computing · 90% Distributed systems · 5% Processor architecture and microarchitecture · 3% |
Topics — the 29 heaviest of 32, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Concurrent programming
transactional memory |
0.2 | 2 | 2011 | Transaction communicators: enabling cooperation among concurrent transactions · PPoPP 2011 Hybrid transactional memory · ASPLOS 2006 |
Programming languages and type systems
type systems |
0.2 | 2 | 2011 | Type checking modular multiple dispatch with parametric polymorphism and multiple inheritance · OOPSLA 2011 Object-oriented units of measurement · OOPSLA 2004 |
Concurrent programming › transactional memory
software transactional memory |
0.2 | 3 | 2006 | A flexible framework for implementing software transactional memory · OOPSLA 2006 Hybrid transactional memory · ASPLOS 2006 Software transactional memory for dynamic-sized data structures · PODC 2003 |
Concurrent programming › synchronization
reader-writer locks |
0.2 | 1 | 2013 | NUMA-aware reader-writer locks · PPoPP 2013 |
Concurrent programming
synchronization |
0.2 | 1 | 2013 | NUMA-aware reader-writer locks · PPoPP 2013 |
Parallel and multicore computing › transactional memory
hardware transactional memory |
0.2 | 1 | 2013 | Using hardware transactional memory to correct and simplify and readers-writer lock algorithm · PPoPP 2013 |
Parallel and multicore computing › synchronization
reader-writer locks |
0.2 | 1 | 2013 | Using hardware transactional memory to correct and simplify and readers-writer lock algorithm · PPoPP 2013 |
Parallel and multicore computing
synchronization |
0.2 | 1 | 2013 | Using hardware transactional memory to correct and simplify and readers-writer lock algorithm · PPoPP 2013 |
Programming languages and type systems › type systems › polymorphism
parametric polymorphism |
0.1 | 2 | 2011 | Type checking modular multiple dispatch with parametric polymorphism and multiple inheritance · OOPSLA 2011 Object-oriented units of measurement · OOPSLA 2004 |
Concurrent programming › non-blocking algorithms
lock-free data structures |
0.1 | 3 | 2005 | Nonblocking memory management support for dynamic-sized data structures · ACM Trans. Comput. Syst. 2005 Bringing practical lock-free synchronization to 64-bit applications · PODC 2004 Dynamic-sized lock-free data structures · PODC 2002 |
Concurrent programming
concurrent data structures |
0.1 | 2 | 2007 | SNZI: scalable NonZero indicators · PODC 2007 Formal Verification of a Lazy Concurrent List-Based Set Algorithm · CAV 2006 |
Programming languages and type systems › type checking
modular typechecking |
0.1 | 1 | 2011 | Type checking modular multiple dispatch with parametric polymorphism and multiple inheritance · OOPSLA 2011 |
Programming languages and type systems › method dispatch
multiple dispatch |
0.1 | 1 | 2011 | Type checking modular multiple dispatch with parametric polymorphism and multiple inheritance · OOPSLA 2011 |
Program verification › concurrent program verification
concurrent data structure verification |
0.1 | 1 | 2006 | Formal Verification of a Lazy Concurrent List-Based Set Algorithm · CAV 2006 |
Concurrent programming › transactional memory
hybrid transactional memory |
0.1 | 1 | 2006 | Hybrid transactional memory · ASPLOS 2006 |
Concurrent programming › atomicity
linearizability |
0.1 | 1 | 2006 | Formal Verification of a Lazy Concurrent List-Based Set Algorithm · CAV 2006 |
Operating systems › resource management › memory management
dynamic memory allocation |
0.1 | 1 | 2005 | Nonblocking memory management support for dynamic-sized data structures · ACM Trans. Comput. Syst. 2005 |
Programming languages and type systems › type systems
dimensional analysis |
0.0 | 1 | 2004 | Object-oriented units of measurement · OOPSLA 2004 |
Programming languages and type systems › object-oriented programming
metaclasses |
0.0 | 1 | 2004 | Object-oriented units of measurement · OOPSLA 2004 |
Concurrent programming › synchronization
non-blocking synchronization |
0.0 | 1 | 2004 | Bringing practical lock-free synchronization to 64-bit applications · PODC 2004 |
Concurrent programming › non-blocking algorithms
non-blocking data structures |
0.0 | 1 | 2003 | Software transactional memory for dynamic-sized data structures · PODC 2003 |
Programming languages and type systems › concurrent programming languages
language constructs for concurrency |
0.0 | 1 | 2011 | Transaction communicators: enabling cooperation among concurrent transactions · PPoPP 2011 |
Programming languages and type systems › object-oriented programming
multiple inheritance |
0.0 | 1 | 2011 | Type checking modular multiple dispatch with parametric polymorphism and multiple inheritance · OOPSLA 2011 |
Concurrent programming
memory reclamation |
0.0 | 1 | 2002 | Dynamic-sized lock-free data structures · PODC 2002 |
Transaction processing and concurrency control
transactional memory |
0.0 | 1 | 2007 | SNZI: scalable NonZero indicators · PODC 2007 |
Programming languages and type systems › object-oriented programming
java |
0.0 | 1 | 2006 | A flexible framework for implementing software transactional memory · OOPSLA 2006 |
Memory systems
memory management |
0.0 | 1 | 2005 | Nonblocking memory management support for dynamic-sized data structures · ACM Trans. Comput. Syst. 2005 |
Distributed systems
consistency models |
0.0 | 1 | 1996 | Eventually-Serializable Data Services · PODC 1996 |
Distributed systems
fault tolerance |
0.0 | 1 | 1996 | Eventually-Serializable Data Services · PODC 1996 |
Methods — techniques the papers use, named apart from their topics
performance evaluation · 0.3lock design · 0.3hardware transactional memory · 0.3nonblocking implementation · 0.1linearizability · 0.1type safety proof · 0.1symmetric multiple dispatch · 0.1software transactional memory · 0.1dependency tracking · 0.1compiler support · 0.1transactional memory · 0.1lock-free synchronization · 0.1hazard pointers · 0.1partial order specification · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Theory Meets Practice in the Algorand Blockchain (Invited Talk)abstractRobust and effective distributed systems require good theory and good engineering, not separately but in concert: user requirements and system constraints are not merely implementation details but often must inform the design of algorithms for such systems. Blockchains are an excellent example. The heart of a blockchain is its (Byzantine) consensus protocol, and consensus protocols have been extensively studied in the theory community for decades. But traditional consensus protocols are not directly applicable to blockchains, which have, or hope to have, millions of participants. Furthermore, public blockchains, which allow anyone to participate, must have some mechanism to guarantee the security of the protocol, and traditional fault models do not adequately capture the assumptions of such mechanisms. In this talk, I will discuss these and other ways in which theory and practice meet in the context of the Algorand blockchain, and how Algorand is able to achieve high transaction throughput with low latency. Victor Luchangco |
OPODIS | 1 |
| 2018 | BQ: A Lock-Free Queue with BatchingabstractConcurrent data structures provide fundamental building blocks for concurrent programming. Standard concurrent data structures may be extended by allowing a sequence of operations to be submitted as a batch for later execution. A sequence of such operations can then be executed more efficiently than the standard execution of one operation at a time. In this paper we develop a novel algorithmic extension to the prevalent FIFO queue data structure that exploits such batching scenarios. An implementation in C++ on a multicore demonstrates a significant performance improvement of up to 16x (depending on batch lengths), compared to previous queue implementations. Gal Sela 0001, Alex Kogan, Yossi Lev, Victor Luchangco, Erez Petrank |
SPAA | 4 |
| 2017 | Extending Transactional Memory with Atomic DeferralabstractThis paper introduces atomic deferral, an extension to TM that allows programmers to move long-running or irrevocable operations out of a transaction while maintaining serializability: the transaction and its de- ferred operation appear to execute atomically from the perspective of other transactions. Thus, program- mers can adapt lock-based programs to exploit TM with relatively little effort and without sacrificing scalability by atomically deferring the problematic operations. We demonstrate this with several use cases for atomic deferral, as well as an in-depth analysis of its use on the PARSEC dedup benchmark, where we show that atomic deferral enables TM to be competitive with well-designed lock-based code. Tingzhe Zhou, Victor Luchangco, Michael F. Spear |
OPODIS | 2 |
| 2017 | Hand-Over-Hand Transactions with Precise Memory ReclamationabstractIn this paper, we introduce revocable reservations, a transactional memory mechanism to reserve locations in one transaction and check whether they are unchanged in a subsequent transaction without preventing reserved locations from being reclaimed in the interim. We describe several implementations of revocable reservations, and show how to use revocable reservations to implement lists and trees with a transactional analog to hand-over-hand locking. Our evaluation of these data structures shows that revocable reservations allow precise and immediate reclamation within transactional data structures, without sacrificing scalability or introducing excessive latency. Tingzhe Zhou, Victor Luchangco, Michael F. Spear |
SPAA | 2 |
| 2017 | Brief Announcement: Extending Transactional Memory with Atomic DeferralabstractAtomic deferral is a language-level mechanism for transactional memory (TM) that enables programmers to move output and long-running operations out of a transaction's body without sacrificing serializability: the deferred operation appears to execute as part of its parent transaction, even though it does not make use of TM. Tingzhe Zhou, Victor Luchangco, Michael F. Spear |
SPAA | 2 |
| 2016 | Investigating the Performance of Hardware Transactions on a Multi-Socket MachineabstractThe introduction of hardware transactional memory (HTM) into commercial processors opens a door for designing and implementing scalable synchronization mechanisms. One example for such a mechanism is transactional lock elision (TLE), where lock-based critical sections are executed concurrently using hardware transactions. So far, the effectiveness of TLE and other HTM-based mechanisms has been assessed mostly on small, single-socket machines. This paper investigates the behavior of hardware transactions on a large two-socket machine. Using TLE as an example, we show that a system can scale as long as all threads run on the same socket, but a single thread running on a different socket can wreck performance. We identify the reason for this phenomenon, and present a simple adaptive technique that overcomes this problem by throttling threads as necessary to optimize system performance. Using extensive evaluation of multiple microbenchmarks and real applications, we demonstrate that our technique achieves the full performance of the system for workloads that scale across sockets, and avoids the performance degradation that cripples TLE for workloads that do not. Trevor Brown 0001, Alex Kogan, Yossi Lev, Victor Luchangco |
SPAA | 4 |
| 2014 | Foreword: Parallelism in Algorithms and Architectures
Geppino Pucci, Victor Luchangco, Rajmohan Rajaraman |
Theory Comput. Syst. | 2 |
| 2013 | Fine-Grained Function Visibility for Multiple Dispatch with Multiple Inheritance
Jieung Kim, Sukyoung Ryu, Victor Luchangco, Guy L. Steele Jr. |
APLAS | 3 |
| 2013 | Mindicators: A Scalable Approach to QuiescenceabstractWe introduce the Mindicator, a new shared object that is optimized for querying the minimum value of a set of values proposed by several processes. A mindicator may hold at most one value per process. This interface is designed for use in shared memory runtime systems, such as garbage collectors, software transactional memory (TM), and operating system kernels. We introduce linearizable and relaxed mindicator implementations, both of which are lock-free. Our algorithms employ a tree structure, where querying the minimum element takes constant time, and adding and removing elements from the set does not hinder scalability. In microbenchmarks and a synthetic TM workload, we show that both provide good scalability on the x86 and SPARC platforms. Yujie Liu 0003, Victor Luchangco, Michael F. Spear |
ICDCS | 2 |
| 2013 | NUMA-aware reader-writer locksabstractNon-Uniform Memory Access (NUMA) architectures are gaining importance in mainstream computing systems due to the rapid growth of multi-core multi-chip machines. Extracting the best possible performance from these new machines will require us to revisit the design of the concurrent algorithms and synchronization primitives which form the building blocks of many of today's applications. This paper revisits one such critical synchronization primitive -- the reader-writer lock. Irina Calciu, David Dice, Yossi Lev, Victor Luchangco, Virendra J. Marathe, Nir Shavit |
PPoPP | 4 |
| 2013 | Using hardware transactional memory to correct and simplify and readers-writer lock algorithmabstractDesigning correct synchronization algorithms is notoriously difficult, as evidenced by a bug we have identified that has apparently gone unnoticed in a well-known synchronization algorithm for nearly two decades. We use hardware transactional memory (HTM) to construct a corrected version of the algorithm. This version is significantly simpler than the original and furthermore improves on it by eliminating usage constraints and reducing space requirements. Performance of the HTM-based algorithm is competitive with the original in "normal" conditions, but it does suffer somewhat under heavy contention. We successfully apply some optimizations to help close this gap, but we also find that they are incompatible with known techniques for improving progress properties. We discuss ways in which future HTM implementations may address these issues. Finally, although our focus is on how effectively HTM can correct and simplify the algorithm, we also suggest bug fixes and workarounds that do not depend on HTM. David Dice, Yossi Lev, Yujie Liu 0003, Victor Luchangco, Mark Moir |
PPoPP | 4 |
| 2013 | Towards formally specifying and verifying transactional memoryabstractAbstract Over the last decade, great progress has been made in developing practical transactional memory (TM) implementations, but relatively little attention has been paid to precisely specifying what it means for them to be correct, or formally proving that they are. In this paper, we present TMS1 (Transactional Memory Specification 1), a precise specification of correct behaviour of a TM runtime library. TMS1 targets TM runtimes used to implement transactional features in an unmanaged programming language such as C or C++. In such contexts, even transactions that ultimately abort must observe consistent states of memory; otherwise, unrecoverable errors such as divide-by-zero may occur before a transaction aborts, even in a correct program in which the error would not be possible if transactions were executed atomically. We specify TMS1 precisely using an I/O automaton (IOA). This approach enables us to also model TM implementations using IOAs and to construct fully formal and machine-checked correctness proofs for them using well established proof techniques and tools. We outline key requirements for a TM system. To avoid precluding any implementation that satisfies these requirements, we specify TMS1 to be as general as we can, consistent with these requirements. The cost of such generality is that the condition does not map closely to intuition about common TM implementation techniques, and thus it is difficult to prove that such implementations satisfy the condition. To address this concern, we present TMS2, a more restrictive condition that more closely reflects intuition about common TM implementation techniques. We present a simulation proof that TMS2 implements TMS1, thus showing that to prove that an implementation satisfies TMS1, it suffices to prove that it satisfies TMS2. We have formalised and verified this proof using the PVS specification and verification system. Simon Doherty, Lindsay Groves, Victor Luchangco, Mark Moir |
Formal Aspects Comput. | 3 |
| 2012 | A Framework for Formally Verifying Software Transactional Memory Algorithms
Mohsen Lesani, Victor Luchangco, Mark Moir |
CONCUR | 2 |
| 2011 | Type checking modular multiple dispatch with parametric polymorphism and multiple inheritanceabstractIn previous work, we presented rules for defining overloaded functions that ensure type safety under symmetric multiple dispatch in an object-oriented language with multiple inheritance, and we showed how to check these rules without requiring the entire type hierarchy to be known, thus supporting modularity and extensibility. In this work, we extend these rules to a language that supports parametric polymorphism on both classes and functions. Eric E. Allen, Justin Hilburn, Scott Kilpatrick, Victor Luchangco, Sukyoung Ryu, David Chase, Guy L. Steele Jr. |
OOPSLA | 4 |
| 2011 | Transaction communicators: enabling cooperation among concurrent transactionsabstractIn this paper, we propose to extend transactional memory with transaction communicators, special objects through which concurrent transactions can communicate: changes by one transaction to a communicator can be seen by concurrent transactions before the first transaction commits. Although isolation of transactions is compromised by such communication, we constrain the effects of this compromise by tracking dependencies among transactions, and preventing any transaction from committing unless every transaction whose changes it saw also commits. In particular, mutually dependent transactions must commit or abort together, and transactions that do not communicate remain isolated. To help programmers synchronize accesses to communicators, we also provide special communicator-isolating transactions, which ensure isolation even for accesses to communicators. We propose language features to help programmers express the communicator constructs. We implemented a novel communicators-enabled STM runtime in the Maxine VM. Our preliminary evaluation demonstrates that communicators can be used in diverse settings to improve the performance of transactional programs, and to empower programmers with the ability to safely express within transactions important programming idioms that fundamentally require compromise of transaction isolation (e.g., CSP-style synchronous communication). Victor Luchangco, Virendra J. Marathe |
PPoPP | 1 |
| 2010 | Integrating coercion with subtyping and multiple dispatch
J. J. Hallett, Victor Luchangco, Sukyoung Ryu, Guy L. Steele Jr. |
Sci. Comput. Program. | 2 |
| 2009 | Scalable reader-writer locksabstractWe present three new reader-writer lock algorithms that scale under high read-only contention. Many previous reader-writer locks suffer significant degradation when many readers attempt to acquire the lock concurrently, even though they are all allowed to hold the lock at the same time. In contrast, our locks scale almost perfectly when there is only read contention on a 4-chip system with a total of 256 hardware threads. Yossi Lev, Victor Luchangco, Marek Olszewski |
SPAA | 2 |
| 2009 | Nonblocking k -Compare-Single-Swap
Victor Luchangco, Mark Moir, Nir Shavit |
Theory Comput. Syst. | 1 |
| 2008 | Efficient Large Almost Wait-Free Single-Writer Multireader Atomic Registers
Andrew Lutomirski, Victor Luchangco |
OPODIS | 2 |
| 2008 | Against lock-based semantics for transactional memoryabstractIn this position paper, I argue that transactional memory should not be specified in terms of locks. In particular, the semantics of transactional memory in the face of nontransactional access, weak memory consistency guarantees and compiler transformations should not be determined by the behaviors exhibited by lock-based implementations. Specifying transactional behavior in terms of locks would repeat mistakes made in the database community and likely result in specifications as inscrutable to programmers as the memory consistency models that proliferated in the 1990s. It would undercut the promise of transactional memory to free us from the tyranny of lock-based programming and the fragile programs that result, a promise based on the potential for transactions to provide a measure of modularity for concurrent programs. We should strive to preserve that potential as we relax transactional guarantees to admit more efficient implementations. Victor Luchangco |
SPAA | 1 |
| 2007 | SNZI: scalable NonZero indicatorsabstractWe introduce the SNZI shared object, which is related to traditional shared counters, but has weaker semantics. We also introduce a resettable version of SNZI called SNZI-R. We present implementations that are scalable, linearizable, nonblocking, and fast in the absence of contention, properties that are difficult or impossible to achieve simultaneously with the stronger semantics of traditional counters. Our primary motivation in introducing SNZI and SNZI-R is to use them to improve the performance and scalability of software and hybrid transactional memory systems. We present performance experiments showing that our implementations have excellent performance characteristics for this purpose. Faith Ellen, Yossi Lev, Victor Luchangco, Mark Moir |
PODC | 3 |
| 2007 | A Simple Optimistic Skiplist Algorithm
Maurice Herlihy, Yossi Lev, Victor Luchangco, Nir Shavit |
SIROCCO | 3 |
| 2006 | Hybrid transactional memoryabstractTransactional memory (TM) promises to substantially reduce the difficulty of writing correct, efficient, and scalable concurrent programs. But "bounded" and "best-effort" hardware TM proposals impose unreasonable constraints on programmers, while more flexible software TM implementations are considered too slow. Proposals for supporting "unbounded" transactions in hardware entail significantly higher complexity and risk than best-effort designs.We introduce Hybrid Transactional Memory (HyTM), an approach to implementing TMin software so that it can use best effort hardware TM (HTM) to boost performance but does not depend on HTM. Thus programmers can develop and test transactional programs in existing systems today, and can enjoy the performance benefits of HTM support when it becomes available.We describe our prototype HyTM system, comprising a compiler and a library. The compiler allows a transaction to be attempted using best-effort HTM, and retried using the software library if it fails. We have used our prototype to "transactify" part of the Berkeley DB system, as well as several benchmarks. By disabling the optional use of HTM, we can run all of these tests on existing systems. Furthermore, by using a simulated multiprocessor with HTM support, we demonstrate the viability of the HyTM approach: it can provide performance and scalability approaching that of an unbounded HTM implementation, without the need to support all transactions with complicated HTM support. Peter Damron, Alexandra Fedorova, Yossi Lev, Victor Luchangco, Mark Moir, Daniel Nussbaum |
ASPLOS | 4 |
| 2006 | Formal Verification of a Lazy Concurrent List-Based Set Algorithm
Robert Colvin, Lindsay Groves, Victor Luchangco, Mark Moir |
CAV | 3 |
| 2006 | A Hierarchical CLH Queue Lock
Victor Luchangco, Daniel Nussbaum, Nir Shavit |
Euro-Par | 1 |
| 2006 | A flexible framework for implementing software transactional memoryabstractWe describe DSTM2, a Java™ software library that provides a flexible framework for implementing object-based software transactional memory (STM). The library uses transactional factories to transform sequential (unsynchronized) classes into atomic (transactionally synchronized) ones, providing a substantial improvement over the awkward programming interface of our previous DSTM library. Furthermore, researchers can experiment with alternative STM mechanisms by providing their own factories. We demonstrate this flexibility by presenting two factories: one that uses essentially the same mechanisms as the original DSTM (with some enhancements),and another that uses a completely different approach.Because DSTM2 is packaged as a Java library, a wide range of programmers can easily try it out, and the community can begin to gain experience with transactional programming. Furthermore, researchers will be able to use the body of transactional programs that arises from this community experience to test and evaluate different STM mechanisms simply by supplying new transactional factories. We believe that this flexible approach will help to build consensus about the best ways to implement transactions, and will avoid the premature "lock-in" that may arise if STM mechanisms are baked into compilers before such experimentation is done. Maurice Herlihy, Victor Luchangco, Mark Moir |
OOPSLA | 2 |
| 2005 | A Lazy Concurrent List-Based Set Algorithm
Steve Heller, Maurice Herlihy, Victor Luchangco, Mark Moir, William N. Scherer III, Nir Shavit |
OPODIS | 3 |
| 2005 | Obstruction-Free Algorithms Can Be Practically Wait-Free
Faith Ellen, Victor Luchangco, Mark Moir, Nir Shavit |
DISC | 2 |
| 2005 | Obstruction-Free Step Complexity: Lock-Free DCAS as an Example
Faith Ellen, Victor Luchangco, Mark Moir, Nir Shavit |
DISC | 2 |
| 2005 | Nonblocking memory management support for dynamic-sized data structuresabstractConventional dynamic memory management methods interact poorly with lock-free synchronization. In this article, we introduce novel techniques that allow lock-free data structures to allocate and free memory dynamically using any thread-safe memory management library. Our mechanisms are lock-free in the sense that they do not allow a thread to be prevented from allocating or freeing memory by the failure or delay of other threads. We demonstrate the utility of these techniques by showing how to modify the lock-free FIFO queue implementation of Michael and Scott to free unneeded memory. We give experimental results that show that the overhead introduced by such modifications is moderate, and is negligible under low contention. Maurice Herlihy, Victor Luchangco, Paul A. Martin, Mark Moir |
ACM Trans. Comput. Syst. | 2 |
| 2004 | Formal Verification of a Practical Lock-Free Queue Algorithm
Simon Doherty, Lindsay Groves, Victor Luchangco, Mark Moir |
FORTE | 3 |
| 2004 | Object-oriented units of measurementabstractPrograms that manipulate physical quantities typically represent these quantities as raw numbers corresponding to the quantities' measurements in particular units (e.g., a length represented as a number of meters). This approach eliminates the possibility of catching errors resulting from adding or comparing quantities expressed in different units (as in the Mars Climate Orbiter error [11]), and does not support the safe comparison and addition of quantities of the same dimension. We show how to formulate dimensions and units as classes in a nominally typed object-oriented language through the use of statically typed metaclasses. Our formulation allows both parametric and inheritance poly-morphism with respect to both dimension and unit types. It also allows for integration of encapsulated measurement systems, dynamic conversion factors, declarations of scales (including nonlinear scales) with defined zeros, and nonconstant exponents on dimension types. We also show how to encapsulate most of the "magic machinery" that handles the algebraic nature of dimensions and units in a single meta-class that allows us to treat select static types as generators of a free abelian group. Eric E. Allen, David Chase, Victor Luchangco, Jan-Willem Maessen, Guy L. Steele Jr. |
OOPSLA | 3 |
| 2004 | Bringing practical lock-free synchronization to 64-bit applicationsabstractMany lock-free data structures in the literature exploit techniques that are possible only because state-of-the-art 64-bit processors are still running 32-bit operating systems and applications. As software catches up to hardware, "64-bit-clean" lock-free data structures, which cannot use such techniques, are needed.We present several 64-bit-clean lock-free implementations: load-linked/store-conditional variables of arbitrary size, a FIFO queue, and a freelist. In addition to being portable to 64-bit software, our implementations also improve on previous ones in that they are space-adaptive and do not require knowledge of the number of threads that will access them. Simon Doherty, Maurice Herlihy, Victor Luchangco, Mark Moir |
PODC | 3 |
| 2004 | DCAS is not a silver bullet for nonblocking algorithm designabstractDespite years of research, the design of efficient nonblocking algorithms remains difficult. A key reason is that current shared-memory multiprocessor architectures support only single-location synchronisation primitives such as compare-and-swap (CAS) and load-linked/store-conditional (LL/SC). Recently researchers have investigated the utility of double-compare-and-swap (DCAS)--a generalisation of CAS that supports atomic access to two memory locations -- in overcoming these problems. We summarise recent research in this direction and present a detailed case study concerning a previously published nonblocking DCAS-based double-ended queue implementation. Our summary and case study clearly show that DCAS does not provide a silver bullet for nonblocking synchronisation. That is, it does not make the design and verification of even mundane nonblocking data structures with desirable properties easy. Therefore, our position is that while slightly more powerful synchronisation primitives can ave a profound effect on ease of algorithm design and verification, DCAS does not provide sufficient additional power over CAS to justify supporting it in hardware. Simon Doherty, David Detlefs, Lindsay Groves, Christine H. Flood, Victor Luchangco, Paul Alan Martin, Mark Moir, Nir Shavit, Guy L. Steele Jr. |
SPAA | 5 |
| 2003 | Obstruction-Free Synchronization: Double-Ended Queues as an ExampleabstractWe introduce obstruction-freedom, a new nonblocking property for shared data structure implementations. This property is strong enough to avoid the problems associated with locks, but it is weaker than previous nonblocking properties-specifically lock-freedom and wait-freedom-allowing greater flexibility in the design of efficient implementations. Obstruction-freedom admits substantially simpler implementations, and we believe that in practice it provides the benefits of wait-free and lock-free implementations. To illustrate the benefits of obstruction-freedom, we present two obstruction-free CAS-based implementations of double-ended queues (deques); the first is implemented on a linear array, the second on a circular array. To our knowledge, all previous nonblocking deque implementations are based on unrealistic assumptions about hardware support for synchronization, have restricted functionality, or have operations that interfere with operations at the opposite end of the deque even when the deque has many elements in it. Our obstruction-free implementations have none of these drawbacks, and thus suggest that it is much easier to design obstruction-free implementations than lock-free and wait-free ones. We also briefly discuss other obstruction-free data structures and operations that we have implemented. Maurice Herlihy, Victor Luchangco, Mark Moir |
ICDCS | 2 |
| 2003 | Software transactional memory for dynamic-sized data structuresabstractWe propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocking property we consider is obstruction-freedom. Obstruction-freedom is weaker than lock-freedom; as a result, it admits substantially simpler and more efficient implementations. A novel feature of our obstruction-free STM implementation is its use of modular contention managers to ensure progress in practice. We illustrate the utility of our dynamic STM with a straightforward implementation of an obstruction-free red-black tree, thereby demonstrating a sophisticated non-blocking dynamic data structure that would be difficult to implement by other means. We also present the results of simple preliminary performance experiments that demonstrate that an "early release" feature of our STM is useful for reducing contention, and that our STM lends itself to the effective use of modular contention managers. Maurice Herlihy, Victor Luchangco, Mark Moir, William N. Scherer III |
PODC | 2 |
| 2003 | Nonblocking k-compare-single-swapabstractThe current literature o .ers two extremes of nonblocking software synchronization support for concurrent data structure design:intricate designs of specific structures based on single-location operations such as compare-and-swap (CAS), and general-purpose multilocation transactional memory implementations. While the former are sometimes efficient, they are invariably hard to extend and generalize. The latter are .exible and general, but costly. This paper aims at a middle ground:reasonably efficient multilocation operations that are general enough to reduce the design difficulties of algorithms based on CAS alone. We present an obstruction-free implementation of an atomic k-location-compare single-swap (KCSS)operation. KCSS allows for simple nonblocking manipulation of linked data structures by overcoming the key algorithmic difficulty in their design: making sure that while a pointer is being manipulated, neighboring parts of the data structure remain unchanged. Our algorithm is efficient in the common uncontended case: A successful k location KCSS operation requires only two CAS operations, two stores, and 2 k noncached loads when there is no contention. We therefore believe our results lend themselves to efficient and flexible nonblocking manipulation of list-based data structures in today's architectures. Victor Luchangco, Mark Moir, Nir Shavit |
SPAA | 1 |
| 2003 | On the Uncontended Complexity of Consensus
Victor Luchangco, Mark Moir, Nir Shavit |
DISC | 1 |
| 2002 | Dynamic-sized lock-free data structuresabstractWe address the problem of integrating lockfree shared data structures with standard dynamic allocation mechanisms (such as malloc and free). We have two main contributions. The first is the design and experimental analysis of two dynamic-sized lockfree FIFO queue implementations, which extend Michael and Scott’s previous implementation by allowing unused memory to be freed. We compare our dynamic-sized implementations to the original on 16-processor and 64-processor multiprocessors. Our experimental results indicate that the performance penalty for making the queue dynamic-sized is modest, and is negligible when contention is not too high. These results were achieved by applying a solution to the Repeat Offender Problem (ROP), which we recently posed and solved. Our second contribution is another application of ROP solutions. Specifically, we show how to use any ROP solution to achieve a general methodology for transforming lockfree data structures that rely on garbage collection into ones that use explicit storage reclamation. Maurice Herlihy, Victor Luchangco, Paul A. Martin, Mark Moir |
PODC | 2 |
| 2002 | The Repeat Offender Problem: A Mechanism for Supporting Dynamic-Sized, Lock-Free Data Structures
Maurice Herlihy, Victor Luchangco, Mark Moir |
DISC | 2 |
| 2001 | Modeling weakly consistent memories with locksabstractNo abstract available. Victor Luchangco |
SPAA | 1 |
| 1999 | Eventually-Serializable Data Services
Alan D. Fekete, David Gupta, Victor Luchangco, Nancy A. Lynch, Alexander A. Schwarzmann |
Theor. Comput. Sci. | 3 |
| 1998 | Computation-Centric Memory ModelsabstractWe present a computation-centric theory of memory models.Unlike traditional processor-centric models, computation-centric models focus on the logical dependencies among instructions rather than the processor that happens to execute them.This theory allows us to define what a memory model is, and to investigate abstract properties of memory models.In particular, we focus on constructibility, which is a necessary property of those models that can be implemented exactly by an online algorithm.For a nonconstructible model, we show that there is a natural way to define the constructible version of that model.We explore the implications of constructibility in the context of dag-consistent memory models, which do not require that memory locations be serialized.The strongest dag-consistent model, called NN-dag consistency, is not constructible.However, its constructible version is equivalent to a model that we call locution consistency, in which each location is serialized independently. Matteo Frigo, Victor Luchangco |
SPAA | 2 |
| 1996 | Computer-Assisted Verification of an Algorithm for Concurrent Timestamps
Tsvetomir P. Petrov, Anna Pogosyants, Stephen J. Garland, Victor Luchangco, Nancy A. Lynch |
FORTE | 4 |
| 1996 | Eventually-Serializable Data ServicesabstractWe present a new specification for distributed data services that trade-off immediate consistency guarantees for improved system availability and efficiency, while ensuring the long-term consistency of the data.An eventually-serializable data service maintains the operations requested in a partial order that gravitates over time towards a total order.It provides clear and unambiguous guarantees about the immediate and long-term behavior of the system.To demonstrate its utility, we present an algorithm, based on one of Ladin, Liskov, Shrira, and Ghemawat [12], that implements this specification.Our algorithm provides the interface of the abstract service, and generalizes their algorithm by allowing general operations and greater flexibility in specifying consistency requirements.We also describe how to use this specification as a building block for applications such as directory services.1 Alan D. Fekete, David Gupta, Victor Luchangco, Nancy A. Lynch, Alexander A. Schwarzmann |
PODC | 3 |
| 1994 | Verifying timing properties of concurrent algorithms
Victor Luchangco, Ekrem Söylemez, Stephen J. Garland, Nancy A. Lynch |
FORTE | 1 |