Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Ning Dong 0002

dblp:31/3173-2 · DBLP profile ↗
← Back
4ranked-venue papers
3as first author
0since 2021 · last 2008
0000-0003-1515-8225ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 88% Integrated circuit design · 12%
Theoretical computer science
1 paper
Algorithms and data structures · 50% Mathematical optimization · 50%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › circuit simulation › reduced-order modeling
nonlinear macromodeling
0.122008
General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Automated nonlinear Macromodelling of output buffers for high-speed digital applications · DAC 2005
Electronic design automation
circuit simulation
0.122008
General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Piecewise polynomial nonlinear model reduction · DAC 2003
Electronic design automation › circuit simulation
model order reduction
0.122008
General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Piecewise polynomial nonlinear model reduction · DAC 2003
Integrated circuit design
analog and mixed-signal circuits
0.112008
General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › design representation
behavioral modeling
0.112008
General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation
signal integrity
0.112005
Automated nonlinear Macromodelling of output buffers for high-speed digital applications · DAC 2005
Electronic design automation › circuit simulation › model order reduction
nonlinear model reduction
0.012003
Piecewise polynomial nonlinear model reduction · DAC 2003
Mathematical optimization › iterative methods
krylov subspace methods
0.012008
General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Algorithms and data structures
numerical algorithms
0.012008
General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation
timing analysis
0.012005
Automated nonlinear Macromodelling of output buffers for high-speed digital applications · DAC 2005

Methods — techniques the papers use, named apart from their topics

proper orthogonal decomposition · 0.2piecewise-polynomial representation · 0.2krylov subspace projection · 0.2black-box modelling · 0.1SPICE-level extraction · 0.1polynomial model reduction · 0.0piecewise polynomial approximation · 0.0
YearPublicationVenuePosition
2008 General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations
abstract
We present algorithms for automated macromodeling of nonlinear mixed-signal system blocks. A key feature of our methods is that they automate the generation of general-purpose macromodels that are suitable for a wide range of time- and frequency-domain analyses important in mixed-signal design flows. In our approach, a nonlinear circuit or system is approximated using piecewise-polynomial (PWP) representations. Each polynomial system is reduced to a smaller one via weakly nonlinear polynomial model-reduction methods. Our approach, dubbed PWP, generalizes recent trajectory-based piecewise-linear approaches and ties them with polynomial-based model-order reduction, which inherently captures stronger nonlinearities within each region. PWP-generated macromodels not only reproduce small-signal distortion and intermodulation properties well but also retain fidelity in large-signal transient analyses. The reduced models can be used as drop-in replacements for large subsystems to achieve fast system-level simulation using a variety of time- and frequency-domain analyses (such as dc, ac, transient, harmonic balance, etc.). For the polynomial reduction step within PWP, we also present a novel technique [dubbed multiple pseudoinput (MPI)] that combines concepts from proper orthogonal decomposition with Krylov-subspace projection. We illustrate the use of PWP and MPI with several examples (including op-amps and I/O buffers) and provide important implementation details. Our experiments indicate that it is easy to obtain speedups of about an order of magnitude with push-button nonlinear macromodel-generation algorithms.
Ning Dong 0002, Jaijeet S. Roychowdhury
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2007 Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods
abstract
We present a fundamentally new approach, ADME, for extracting highly accurate delay models of a wide variety of digital gates. The technique is based on trajectory-piecewise automated nonlinear macromodelling methods adapted from the mixed-signal/RF domain. Advantages over prior current-source models include rapid automated extraction from SPICE-level netlists, transparent retargetability to different design styles and technologies, and the ability to correctly and holistically account for complex input waveform shapes, nonlinear and linear loading, multiple input switching, effects of internal state, multiple I/Os, supply droop and substrate interference. We validate ADME on a variety of digital gates, including multi-input NAND, NOR, XOR gates, a full adder, a multilevel cascade of gates and a sequential latch. Our results confirm excellent model accuracy at the detailed waveform level and testify to the promise of ADME for sustainable gate delay modelling at nanoscale technologies.
S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury
ASP-DAC2
2005 Automated nonlinear Macromodelling of output buffers for high-speed digital applications
abstract
We present applications of a recently developed automated nonlinear macromodelling approach to the important problem of macromodelling high-speed output buffers/drivers. Good nonlinear macromodels of such drivers are essential for fast signal-integrity and timing analysis in high-speed digital design. Unlike traditional black-box modelling techniques, our approach extracts nonlinear macromodels of digital drivers automatically from SPICE-level descriptions. Thus it can naturally capture transistor-level nonlinearities in the macromodels, resulting in far more accurate signal integrity analysis, while retaining significant speedups. We demonstrate the technique by automatically extracting macromodels for two typical digital drivers. Using the macromodel, we obtain about 8x speedup in average with excellent accuracy in capturing different loading effects, crosstalk, simultaneous switching noise (SSN), etc.
Ning Dong 0002, Jaijeet S. Roychowdhury
DAC1
2003 Piecewise polynomial nonlinear model reduction
abstract
We present a novel, general approach towards model-order reduction (MOR) of nonlinear systems that combines good global and local approximation properties. The nonlinear system is first approximated as piecewise polynomials over a number of regions, following which each region is reduced via polynomial model-reduction methods. Our approach, dubbed PWP, generalizes recent piecewise linear approaches and ties them with polynomial-based MOR, thereby combining their advantages. In particular, reduced models obtained by our approach reproduce small-signal distortion and intermodulation properties well, while at the same time retaining fidelity in large-swing and large-signal analyses, e.g., transient simulations. Thus our reduced models can be used as drop-in replacements for time-domain as well as frequency-domain simulations, with small or large excitations. By exploiting sparsity in system polynomial coefficients, we are able to make the polynomial reduction procedure linear in the size of the original system. We provide implementation details and illustrate PWP with an example.
Ning Dong 0002, Jaijeet S. Roychowdhury
DAC1