Random redundant data storage strategies have proven to be a good choice for efficient data storage in multimedia servers. These strategies lead to a retrieval problem in which it is decided for each requested data block which disk to use for its retrieval. In this paper, we give a complexity classification of retrieval problems for random redundant storage.

We derive the guaranteed throughput of a multizone disk that repeatedly handles batches of n requests of constant size. Using this guaranteed throughput in the design of multimedia systems, one can admit more streams or get smaller buffer requirements and guaranteed response times than when an existing lower bound is used. We consider the case that nothing can be assumed about the location of the requests on the disk. Furthermore, we assume that successive batches are handled one after the other, where the n requests in a batch are retrieved using a SCAN-based sweep strategy. We show that we only have to consider two successive batches to determine the guaranteed throughput. Using this, we can compute the guaranteed throughput by determining a maximum-weighted path in a directed acyclic graph in O(z/sub max//sup 3/n/sup 2/) time, where z/sub max/ is the number of zones of the disk.

The size of the test vector set forms a significant factor in the overall production costs of ICs, as it defines the test application time and the required pin memory size of the test equipment. Large core-based ICs often require a very large test vector set for a high test coverage. This paper deals with the design of scan chains as transport mechanism for test patterns from IC pins to embedded cores and vice versa. The number of pins available to accommodate scan test is given, as well as the number of scan test patterns and scannable flip flops of each core. We present and analyze three scan chain architectures for core-based ICs, which aim at a minimum test vector set size. We give experimental results of the three architectures for an industrial IC. Furthermore we analyze the test time consequences of reusing cores with fixed internal scan chains in multiple ICs with varying design parameters.